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TDA4VM: questions about SAFETY_ERR, RTC and DDR_RET

user6283181
Prodigy 110 points
Part Number: TDA4VM

Hi, 

We are using TDA4 with TPS6594X-Q1. We have some questions about the TDA4 work mode, and power supply.

1, LEO-A GPIO7: input < -- nERR_MCU_SAFETY (SOC_SAFETY_ERRn is optional) 

This pin is for function safety. Which state will PMIC and TDA4 will go into once PMIC get this signal?

What happens, and then MCU/ SoC send out this signal?  

2, LEO-A OSC32K port: RTC crystal interface.

These pins are crystal connection pins for RTC.

If there is no RTC, PMIC  and TDA4’s SAFETY, WATCHDOG functions will be affected?

we need not calendar function. 

3, LEO-B GPIO4: OD output  -- >  SoC DDR_RET_1V1

what is this signal sequence requirement?

Under which work mode, DDR retention function is needed?

Does SoC need change this output after startup? 

  • 0
    TI__Expert 8165 points

    Hi,

    I'll ask a LeoPMIC expert to look into this soon.

    Regards,
    Anand

  • 0 in reply to Anand Mahadevan SS
    Prodigy 110 points

    hello Sir, 

    long time passed, when I can get the right answers?

    thanks! 

  • 0 in reply to user6283181
    TI__Mastermind 48641 points

    Hi, please see my answers/comments below:

    Q1: LEO-A GPIO7: input < -- nERR_MCU_SAFETY is for function safety. Which state will PMIC and TDA4 will go into once PMIC get this signal?

    A1: This pin is for the system error count down input signal from the MCU (Active Low). Please search "nERR_MCU" with datasheet to know more detail about this pin; it's not possible to describe it here. 

    Q2: What happens, and then MCU/ SoC send out this signal?  

    A2: Please see section of datasheet: 5.3.11 Error Signal Monitor (ESM).

    Q3: If there is no RTC, PMIC  and TDA4’s SAFETY, WATCHDOG functions will be affected? we need not calendar function. 

    A3: No, RTC is totally independent function, it doesn't have impact to WATCHDOG function.

    Q4: LEO-B GPIO4: OD output  -- >  SoC DDR_RET_1V1; what is this signal sequence requirement?

    A4: This pin is not set in PMIC NVM; it depends on application; please check with TDA4’s related documents. 

    Q5: Under which work mode, DDR retention function is needed?

    A5: Please check with TDA4’s related documents. 

    Q6: Does SoC need change this output after startup? 

    A6: Please check with TDA4’s related documents. 

  • 0 in reply to Phil Yi
    Prodigy 110 points

    Phil, 

    thanks! 

    LEO-B's DDR_RET_1V1 output is not controlled by NVM. 

    How does MCU domain or MAIN Domain LEO-B's GPIO4 output to DDR_RET_1V1? 

    Via LEO's I2C1 port? 

  • 0 in reply to user6283181
    TI__Mastermind 48641 points

      Yes; MCU can setup GPIO4 output to DDR_RET_1V1 via LEO's I2C1 port.