TDA4VM: CSI registers to report status of frames / errors

Hi John,

Could you please give some background? Why are we not using driver?

We can register callbacks in driver to know the error status..

Regards,

Brijesh

Hi Brijesh,

We have no idea about your csi driver, so far we are changing sensor driver to configure our GMSL deserializer, we see that data(on the scope) is coming out of deserializer, but not sure if SoC is able to receive the frames ? Are there any prints I can look for ?

Table 12-19995. CSI_RX_IF Inter-clock Dependencies in the TRM mentions four clocks CSI_RX_MAIN_CLK, CSI_RX_VBUS_CLK, CSI_RX_VP_CLK and CSI_RX_BYTE_CLK

static IssSensorIntfParams imx390SensorIntfPrms = {
0, /*isMultiChannel*/
4, /*numCSI2Lanes*/
1, /*inCsi2VirtualChanNum*/
1, /* isCplxCfgValid */
{
{0, 1}, /* Clock Lane */
{0, 2}, /* data1Lane */
{0, 3}, /* data2Lane */
{0, 4}, /* data3Lane*/
{0, 5}, /* data4Lane */
},
800, /* csi2PhyClk */
0, /*sensorBroadcast*/
0, /*enableFsin*/
};

static IssSensor_CreateParams imx390CreatePrms = {
SENSOR_SONY_IMX390_UB953_D3, /*sensor name*/
0x6, /*i2cInstId*/
{SENSOR_0_I2C_ALIAS, SENSOR_1_I2C_ALIAS, SENSOR_2_I2C_ALIAS, SENSOR_3_I2C_ALIAS}, /*i2cAddrSensor*/
{SER_0_I2C_ALIAS, SER_1_I2C_ALIAS, SER_2_I2C_ALIAS, SER_3_I2C_ALIAS}, /*i2cAddrSer*/
/*IssSensor_Info*/
{
{
IMX390_OUT_WIDTH, /*width*/
IMX390_OUT_HEIGHT-IMX390_META_HEIGHT_AFTER, /*height*/
1, /*num_exposures*/
vx_false_e, /*line_interleaved*/
{
{TIVX_RAW_IMAGE_16_BIT, 11}, /*dataFormat and MSB [0]*/
},
0, /*meta_height_before*/
IMX390_META_HEIGHT_AFTER, /*meta_height_after*/
},
ISS_SENSOR_IMX390_FEATURES, /*features*/
ALGORITHMS_ISS_AEWB_MODE_AEWB, /*aewbMode*/
30, /*fps*/
4, /*numDataLanes*/
{1, 2, 3, 4}, /*dataLanesMap*/
{0, 0, 0, 0}, /*dataLanesPolarity*/
800, /*CSI Clock*/
},
4, /*numChan*/
390, /*dccId*/
};

We have IMX390 GMSL2 cameras with in built ISP and ISP output is 30fps, 640*360 pixels in YUV422 8Bit format and we have 4 lanes from deserializer connected to CSI0

And sensor driver has csi2PhyClk configured as 800 not sure which clock it is out of the four from the TRM table, now we need to know whether CSI is receiving the frames, are there any registers to look for or any prints from csi driver ?

Hello Mahipal,

Please refer to the image sensor documentation I shared with you. All these parameters are explained there.

Parameter "csi2PhyClk" is not used currently. You may set it to 0 or any other value.

Regards,

Mayank

Hi Mayank,

I could not find IssSensorIntfParams in your documentation but IssSensor_Info (part of IssSensor_CreateParams) also has an entry csi_ddr_clock, which is also set to 800.

Where exactly CSI clock needs to be configured ?

Can I know which CSI registers to look for to know the CSI status ?

Please ignore csi_ddr_clock.

We will follow up with register level details.

Hello Manipal,

I am bit confused. 

As per below configuration, the input format is RAW12bit, but you are saying input is YUV422. 

{TIVX_RAW_IMAGE_16_BIT, 11}, /*dataFormat and MSB [0]*/

Please note that if there is format mismatch, capture will not be able to detect input steams and capture data..

Rgds,

Brijesh

Hi Brijesh

Mayank suggestd to use TIVX_RAW_IMAGE_16_BIT, in https://e2e.ti.com/support/processors/f/791/p/879084/3253328#3253328, what am i supposed to use for YUV422 ? Can I know the CSI registers to monitor for ?

Hi Vivek,

Hi Mahipal,

From register dumps, looks like there are no errors. Can you please look at your data type configurations? It should be related to 'YUV422'. Also, please make sure that data is being observed at the input of CSIRX DPHY data lanes.

Thanks & Regards,

Vivek Dhande.

Texas Instruments (India) Pvt Ltd

Hi Vivek,

Vibhor tried the changes you suggested, still it gets blocked at the deque API call, is there anything else to confirm within CSI registers if it is receiving valid data from the deserializer,recognizable by the SoC ?

We do not have a MIPI Analyzer to confirm that the data is valid  

Hi Vivek,

I see the status as "TI Thinks Resolved", it's not resolved yet

Mahipal,

"TI Thinks Resolved" is just a state on a single post.  This thread is still open.  Until we get to "Resolved" state, Vivek and team will continue to work the thread.

John

Hello Vivek,

Please find registers level analysis from Visteon, 

CSI_RX_IF_VBUS2APB_DPHY_STATUS (DPHY Clock and Data Lane mode status):

On Custom Board, CSI_RX_IF_VBUS2APB_DPHY_STATUS value is 0x00222206 before a stream on then DPHY Data lane stop bit is set it to high 0x00333306 and it remains same for the whole cycle which means we received only one packet. 

On EVM, We could see that CSI_RX_IF_VBUS2APB_DPHY_STATUS  value is 0x00222206 before the stream on and once it receives data the DPHY Data lane stop bit is set it to high and the value is  0x00333306. I could see that DPHY Data lane stop bit on and off on the working EVM. So, We should get the same toggle between 0x00222206 and 0x00333306 on the working setup, right?

CSI_RX_IF_VBUS2APB_INTEGRATION_DEBUG:

on EVM, PROT_FSM_STATE is 0x001 which mean WAIT_FOR_PACKET then moving to 0x010(PAYLOAD_DATA) when it receivces data.

on Custome board the register value 0x001 remains same for the whole test cycle.

CSI_RX_IF_VBUS2APB_STREAM0_STATUS:

On EVM, The value is 0x80000113 which means RUNNING is 1(The Stream is enabled), READY_STATE is 1, STREAM_FSM is 1(Expecting control data next). 

on Custom board, The register value is 0x00000100 and it remains same, just Indicates the state of the pushback signal pixel_ready if for this stream.

Could you please give us direction on what could be the issue, and how to approach it, What are the changes we can try at deser or configs? Can we have a list of registers we can monitor if that is not listed here?  

Please find the other register dump analysis bw Custom and EVM,

Hi Vivek,

We didn't see any error from the ERROR or CTRL registers of CSI_RXi, Does it mean we are reciving a valid frame to DPHYi Ports from deserializer?

The registers that we checked below,

CSI_RX_IF_VBUS2APB_ERROR_IRQS_MASK_CFG

CSI_RX_IF_VBUS2APB_DPHY_ERR_STATUS_IRQ

CSI_RX_IF_VBUS2APB_DPHY_ERR_IRQ_MASK_CFG

CSI_RX_IF_VBUS2APB_ERROR_DEBUG

CSI_RX_IF_VBUS2APB_STREAM0_CTRL

CSI_RX_IF_VBUS2APB_STREAM0_STATUS

CSI_RX_IF_VBUS2APB_DPHY_ERR_STATUS_IRQ

Regards,

Jegathesan S

Hi Jegathesan,

If you do not see any error, it does not mean that you are receiving the data.

Can you please make sure that data toggles are being seen on the CSIRX DPHY data lanes?

Also, can you please send the full register dump of all the CSIRX module? These are as follows:

• CSI_RX_IF0_VBUS2APB_WRAP_VBUSP_APB_CSI2RX (0x04504000 to 0x04505000)
• CSI_RX_IF0_RX_SHIM_VBUSP_MMR_CSI2RXIF (0x04500000 to 0x04501000)
• CSI_PSILSS0_MMRS (0x03410000 to 0x03411000)

Thanks & Regards,
Vivek Dhande.

Texas Instruments (India) Pvt Ltd