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Original question:

AM4376: DDR data bus--swapping data lines

AM4376: DDR3 prime bit swapping

Robert Schicke
Prodigy 110 points

Part Number: AM4376
Other Parts Discussed in Thread: TMDSIDK437X

Hi Biser,

The DDR3 section of our board is based off of the schematic and layout of the AM437x Starter Kit and it works fine. In the SK pinout it seems all of the bits within the byte lanes are swapped including the prime "first" bit in each lane. However I just saw the posts "TMDSIDK437X: Single 16-bit DDR3" and "AM4376: AM4376BZDND80" where you say that the prime bit for each byte lane shouldn't be swapped. Is this a problem. What kind of issue could this cause? We are about to do a spin of the board, should we change the layout so that Bit0 of each byte lane isn't swapped? Or should we just leave it as is? I would rather not fix it if it isn't broke.

Thanks,

Bob

  • 0
    TI__Guru* 95321 points

    Bob, I would recommend to keep the prime bit as recommended in the other posts.  It is used during write leveling as feedback to the controller to properly align DQS and the memory clock.  If DQ0 is swapped, you could potential get incorrect feedback, resulting in timing issues which could cause functional failures or compliance issues.   More info about the prime bit can be found in your memory datasheet.  Essentially, the DQ0 of each byte should be aligned with the controller.

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 110 points

    Thanks James. That makes sense.

    I'm trying to understand why the AM347x Starter Kit has only the first bit of the first byte in the original location, while the other 3 are swapped. Is the reason that it doesn't follow that methodology because it is a balanced T topology and doesn't really need leveling? Or is leveling needed in Balanced T and Fly-by?

    Bob

  • 0 in reply to Robert Schicke
    TI__Guru* 95321 points

    Hi Bob, let me get back to you on this.  I'm double checking some info on our DDR PHY.  There may be some provisions in the PHY which may explain this.  

    Regards,

    James

  • 0 in reply to JJD
    TI__Guru* 95321 points

    Hi Bob, sorry for the late reply on this.  We are still in the process of confirming, but we have looked at the PHY and during write leveling, all of the data signals are ORed together, so that any of the DQ bits can be used as the prime bit.  I believe early on in DDR3 life cycle, memory vendors were choosing different bits to be the prime bit in the device, so the PHY designed in the ORing so it can accommodate any of the bits to be the prime bit.  Today, i think most if not all vendors are using DQ0 exclusively. 

    As a consequence of the design in the AM43xx DDR PHY, the requirement to keep the prime bit alignment is not necessary, and thus all bits within a byte can be swapped.  This is the reason why the SK EVM and other designs work fine with write leveling.

    Regards,

    James