OMAP-L138 LCDK, SYSCLK7 is out of range using standard issued GEL file

Robert Wolfe

Other Parts Discussed in Thread: OMAP-L138

Hello,

I'm working with the OMAP-L138 LCDK, setting up PLL values. Using the OMAP-L138 LCDK gel file, I am setting the core to 456 MHz, according to this call:

Set_Core_456MHz() {
device_PLL0(0,18,0,0,1,11,5);
GEL_TextOut("\tPLL0 init done for Core:456MHz, EMIFA:38MHz\n","Output",1,1,1);
}

However, with that value of 5 for PLLDIV7, we end up with a SYSCLK7 value of 76 Mhz, which is greater than the 50 MHz maximum specified in Table 6-5 in SPRS586J OMAP-L138 data sheet, when using the 1.3 V NOM core voltage.

This is a TI supplied gel file, so was it overlooked that these settings result in exceeding the maximum for SYSCLK7 in this case?

Regards,

Robert

over 5 years ago

0 Rahul Prabhu over 5 years ago

TI__Guru** 116170 points

Robert,

Agree with your assessment here. the SYSCLK7 value seems to be a violation and seems to be an error introduced from the 300 Mhz GEL file that was previous supported where the divider would allow SYSCLK7 to be set at 50 Mhz (max). For 456 Mhz (SYSCLK1), you will need to change that divider to 10 to be under the < 50 MHz datasheet recommendation.

However notice that this clock is used as one of the clocks driven into EMAC module on the SOC so you can have an external 50 Mhz crystal that clocks the EMAC so this clock is not used so from software perspective it may not impact EMAC software .

Thanks for bringing this to our attention.

Regards,

Rahul

0 Robert Wolfe over 5 years ago in reply to Rahul Prabhu

Mastermind 7860 points

Thanks for the reply. Yeah, I had sort of seen after posting, that SYSCLK7 is basically a don't-care in my application. Note that the GEL settings for 300 MHz DDR also are erroneous, creating a SYSCLK3 that is greater than maximum.

Regards,

Robert

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OMAP-L138 LCDK, SYSCLK7 is out of range using standard issued GEL file