Hi,
my customer will use UHPI of C5517. They would like to confirm the behavior of the pins after reset release. The chip select signal (EM_SDCAS / UHPI_HCS) in UHPI belongs to Z, High Group immediately after reset release, so they think that High is output from the terminal. Normally, UHPI_HCS is used by connecting it to the CS signal of the host CPU. However, since the CS signal of the HOST CPU is naturally output, signal collision is considered to occur. There are several such signals, but is it necessary to provide an external circuit configuration that does not cause collision by gate control?
If necessary, please tell us which signal should be used to check the gate switching timing. They believe that two gates are required when switching DSPs.
(1) At the transition from reset release to UHPI Boot Mode -> At what timing after Reset release does the UHPI pin setting complete?
(2) When processing is passed from Boot Loader to Main Program -> The timing when the Boot Loader invalidates UHPI (is the terminal state the same as in (1) at this time?) And passes the processing to the main program
Best Regards,
M.Ohhashi