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TDA2P-ACD: How to use two 1-lane Gen2 for PCIe .

Downey Kim
Expert 2675 points
Part Number: TDA2P-ACD
Other Parts Discussed in Thread: TDA2PXEVM

Hi TI team,

My customer want to use two 1-lane Gen2 of PCIe.

TDA2PXEVM is designed with 2-lane Gen2. do you have reference data designed with 1-line Gen2 of PCIe?

To design a two-lane Gen2, can I share a clock? Or do I have to supply each clock?

Thanks,

Downey Kim

  • 0
    TI__Mastermind 18400 points

    Hi Downey Kim,

    TDA2P SoC supports one 100-MHz clock input/output, therefore PCIe PHYs will be clocked by the same clock regardless of the mode - one dual PCIe link, or two single lane PCIe links.

    Thus, external link partners will also share the same clock. Note that there must be a clock buffer for each clock sink (input). I.e. a clock output must not be split to two or more sinks  without buffering.

    Regards,

    Stan