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AM5729: Pru Ethernet Interface in Beaglebone AI

Davide Brunelli
Intellectual 980 points

Part Number: AM5729
Other Parts Discussed in Thread: BEAGLE-3P-BBONE-AI, , TMDSIDK572

Goodmorning,

I write you to have a confirmation about the new Beaglebone AI, .

Looking at the schematics github.com/.../BeagleBone-AI_sch.pdf, do you think it's possible to have the PRU ethernet port enable (with pr1?) in order to achieve industrial ethernet communication. Is it correct?

Thank you.

Best Regards,

Davide Brunelli

  • 0
    TI__Genius 14680 points

    Davide,

    The Beagleboard-AI product does bring some of the PRU-ICSS signals to board headers, but not the full Ethernet MAC interfaces. So depending on the protocol (Ethernet vs. Fieldbus) you may be able to enable.

    Please see , which shows PRU-GPIO, UART, Pulse Capture as available. On beagleboard.org you can see specific details on the interfaces -- .

    For an AM5729 hardware platform from TI with PRU-ICSS Ethernet connectivity, please refer to 

    Best regards,

    Dave

  • 0 in reply to Dave Bell
    Intellectual 980 points

    Hello Dave,

    thank you for your answer. The final purpose of my implementation is an Ethercat master with low jitter and high performances. I studied the schematics of Beaglebone AI:

    The TMDSIDK572 board concerning the ethernet connector J10:

    and the AM572x General Purpose EVM Processor Module, concerning the RJ45 connector P5:

    All the three boards uses exactly the same pins for the ethernet connectors specified above. Beaglebone AI however uses a different PHY.

    Reading the document

    it states that on TMDSIDK572 only connector J3, J5, J6 and J8 can be used as 100MbEthernetPorts on PRU-ICSS.

    I noticed that on TMDSIDK572 connector J3 uses the same pins as J10 one (concerning RXs and TXs) but it has some pins different (AM57XX_PRU1ETH0_MRCLK, AM57XX_PRU1ETH0_RXDV, AM57XX_PRU1ETH_MDCLK, AM57XX_PRU1ETH_MDDATA).

    Here the questions:

    1. Concerning TMDSIDK572, the fact that J10 and J3 share pins does it means that the RMII interface can be enable on these ports and use contemporary? However if J3 connector is used as PRU-ICSS, since PRU implements only MII interface, J10 becomes unavailable with this setting?
    2. Concerning Beaglebone AI and  AM572x General Purpose EVM Processor Module, it looks to me that it's not possible to implement a PRU-ICSS interface since they lack some pru pins that instead are used on connector J3 of board TMDSIDK572. Is it correct?

    Thank you for the patience but for me it's very important to understand these points to avoid to spend money and then find out that the board is not suitable for our application.

    Regards,

    Davide

  • 0 in reply to Davide Brunelli
    Intellectual 980 points

    Hello,

    are there any news?

    Regards,

    Davide

  • 0 in reply to Davide Brunelli
    TI__Genius 14680 points

    Davide,

    The Beaglebone-AI hardware (and AM57 EVM) is such that the CPSW RGMII signals are routed to the Ethernet PHY. While many pins are shared with the PRU-ICSS MII interface they are not directly overlaid with support for selection of the MII. If the PRI-ICSS MII is required, then this is supported on the IDK.

    That said, if you are looking to support EtherCAT Master, then you can confirm with the stack offering you are planning to use to confirm support over the CPSW interface. This would then be still supportable on the Beaglebone-AI.

    Best regards,

    Dave