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Hi champs,
customer need to know if he can change individual "dual channels" A vs B.
Idea is 2x16bit Dual Rank System
Channel A = 16bit
Channel B = 16bit
each channel has its own address/control signals.
He wants to connect to two LPDDR4 memories in this way:
Memory IC1 2x16bit Bus
Channel-A -> Memory IC1.Channel-A und IC1.ChipSelect0 A zu A routing
Channel-B -> Memory IC1.Channel-B und IC1.ChipSelect0 B zu B routing
Memory IC2 2x16bit Bus
Channel-A -> Memory IC2.Channel-B und IC1.ChipSelect1 A zu B routing
Channel-B -> Memory IC2.Channel-A und IC1.ChipSelect1 B zu A routing
According to layout recommendation from TI this seems not to work:
Channel, Byte, and Bit Swapping
All signals, including data and address/control, must be routed 1 to 1 from the DDR controller to the LPDDR4 memory.
Byte swapping across channels or within a channel is not allowed.
Similarly, data bit swapping across byte lanes or within a byte is also not allowed.
In addition, byte lanes 0 and 1 of the DDR controller must be routed to channel A of the LPDDR4 memory,
and byte lanes 2 and 3 of the DDR controller must be routed to channel B of the LPDDR4 memory.
Q: What is background of this statement ? Any ways to realize customers ideas ?
Hi,
I added some more explanations from customer.
His architecture below seems to be important for his design:
I have a 32bit memory controller (AM65xx) and I want to connect it to a 32bit (2x 16bit dual channel) LPDDR4 memory.
See picture LPDDR4 Memory Dual channel
I want to install two 32bit (dual channel) LPDDR4 RAMs in my design.
The design recommendation only speaks of a point-to-point connection memory controller to single RAM,
but what if I want to connect two LPDDR4 memories, one memory to nCS0_A & nCS0_B and the other memory to nCS1_A & nCS1_B.
Or is it not possible?
Since both channels are independent, the memory controller should not care whether A goes to A or A goes to B.
I don't want to exchange the CA Control signals and the DQ signals, just
Channel A x16 (CAx_A, DQ_A [0:15) with
Channel B x16 (CAx_B, DQ_B [0:15]
Pls check!
DJ,
The question seems to be for “dual rank” (two chip selects) topology where each segment (say DQ[15:0], and similarly DQ[31:16]) is connected to two memories, such as in this diagram (from Micron datasheet):
There is also hints in the question of channel swapping (which is also not supported, but seems to no longer part of the question).
Whereas this Micron diagram shows 1 package with 4 die, it seems the customer wants to split the 4 die across 2 packages. Support for Dual Rank (even for 4 dies in one package) has not been validated and is the primary reason we would not recommend/support a dual rank topology. Going a step further, the PCB layout for supporting two packages would be extremely difficult and it is likely not possible to meet timings at all 3 endpoints (2 memories, 1 SoC) and avoid reflections, etc.
The documentation is consistent that only a single rank is supported … the TRM states:
And the layout guideline doc (SPRACI2) states:
On the other hand, the TRM does show a mapping from the AC bus to CS1 in the "DDRSS0 AC Bus Mapping" table. This will be removed in the next revision.
Regards,
Kyle
Dear DJ
thanks for your replay.
On the other hand, the TRM does show a mapping from the AC bus to CS1 in the "DDRSS0 AC Bus Mapping" table. This will be removed in the next Revision.
Is that true, why?
Yes I understand
Note:
Though LPDDR4 SDRAMs pin out 2 separate channels, independent channel use is not
supported by this processor. The ADDR_CTRL signals are replicated for load sharing
purposes and must be connected as shown.
I also don't want to run channel A or B separately, I rather want to run the processor in
32-bit, single-rank LPDDR4 implementation (No ECC). Reference (AM65x / DRA80xM DDR Board Design and Layout Guidelines, page 24)
and the Memory Bus Features: Up to 2 ranks (LPDDR4 only) (SPRUID7D–April 2018–Revised June 2019, page 3769)
complete another LPDDR4 but swap part A and B on the memory so that I can position one memory top and the other bottom.
Schematic as follows
Best regards
Michael
