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AM6526: Want to minimize an error of UART Baud Rate

Hideaki Matsumoto
Genius 9200 points
Part Number: AM6526

Hi,

 

The customer has a question about UART Baud Rate Setting described in Table 12-624 in AM65xx TRM. They want 115.2kbps, but its baud rate error becomes +0.16%.

Is it possible to minimize this error to 0% ?

If the external 48MHz oscillator (not internal PLL) was used as UART input clock, can it be 0% or lower ?

 

Regards,

Hideaki

  • 0
    TI__Genius 10180 points

    Hideaki-san,

    Checking into the spec, the +0.16% jitter error table actually did not include the reference clock error and jitter.  It came from the baud rate generator and internal divider.  As a result it will not be possible to minimize this error to 0% by switching to an external oscillator.

    Have a great day!

    Best Regards,

    Shiou Mei