Can you explain why the power spreadsheet for the 6457 only allows 83M Bytes /sec as the maximum value for the HPI interface? It appears that it should be able to take data at a rate of 40MHz defined by the sum of tw(HSTBH)=10ns + tw(HSTBL)=15ns. So for 16-bit mode it would be limited to 80M Bytes /sec but for 32-bit mode it should be able to achieve 160M Bytes/sec. In this case we're using the Spreadsheet for Power Calculations to alert us of a limitation on the HPI interface datarate, is this correct, or is this limitation false and an arror in the Power estimator?
We will most likely run our logic at 200MHZ (2x the EMIF clock) to provide the tw(HSTBH)=10ns (2 clocks) and tw(HSTBL)=15ns (3clocks) and use 16-bit mode. Our 64-bit EMIF can burst data at 800M Bytes /sec. Because we can send packets of 1518 bytes and the HPI cannot keep up, I will need to implement a 512x32bit FIFO for data to the HPI. Can you confirm this finding for us?
Thank you,
Bryan Busacco.