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AM3358: LCD timing relationship between HSYNC and VSYNC

Brad Caldwell
Genius 12595 points
Part Number: AM3358
Other Parts Discussed in Thread: AM3352,

Dear Champs,

I'm investigating an issue with the AM3352 LCD controller that's related to the timing between HSYNC and VSYNC.

I'm looking at the AM3358 datasheet timing for the LCD controller in raster mode. Figures 7-82 and 7-83 are drawn such that they give the impression that the rising edge and falling edge of VSYNC are aligned with the rising edge of HSYNC.

Here's a screenshot of figure 7-82 that shows this.

However, what's been observed is that the edges of VSYNC are aligned with the falling edge of HSYNC. To verify this, I measured the signals on our AM335x GP EVM. Sure enough, the VSYNC edges align with the falling edges of HSYNC.

Scope capture of HSYNC(green) and VSYNC(yellow) on AM335x GP EVM

Is there a way to have the rising edge of HSYNC line up with the rising edge of VSYNC?

  • 0
    TI__Genius 15310 points

    Hi Brad,

    Can you share what values your device is programming into the RASTER_CTRL and RASTER_TIMING_[0:2] registers?

    Regards,

    Melissa

  • 0 in reply to melissaw
    TI__Genius 12595 points

    Here are the registers values. Note: I booted the EVM using the default SDK image on SD card, no changes to LCD settings.

    root@am335x-evm:~# devmem2 0x4830e028

    /dev/mem opened.

    Memory mapped at address 0xb6f02000.

    Read at address 0x4830E028 (0xb6f02028): 0x06200081

    root@am335x-evm:~# devmem2 0x4830e02c

    /dev/mem opened.

    Memory mapped at address 0xb6fd3000.

    Read at address 0x4830E02C (0xb6fd302c): 0x2626BB10

    root@am335x-evm:~# devmem2 0x4830e030

    /dev/mem opened.

    Memory mapped at address 0xb6ff2000.

    Read at address 0x4830E030 (0xb6ff2030): 0x1D0D05DF

    root@am335x-evm:~# devmem2 0x4830e034

    /dev/mem opened.

    Memory mapped at address 0xb6f36000.

    Read at address 0x4830E034 (0xb6f36034): 0x0200FF00

    root@am335x-evm:~#

     

    Summary:

    28h RASTER_CTRL 0x06200081

    2Ch RASTER_TIMING_0 0x2626BB10

    30h RASTER_TIMING_1 0x1D0D05DF

    34h RASTER_TIMING_2 0x0200FF00

     

  • 0 in reply to Brad Caldwell
    TI__Genius 15310 points

    Hi Brad,

    I think you should be able to shift the HSYNC / VSYNC pulses so that the rising edges align by playing with the hfp, hbp, vfp, and vbp parameters in the RASTER_TIMING_0/1 registers.

    My first recommendation is to increase the hfp (front porch) parameter by the current hsw value and reduce hbp by the same value (to compensate for the hfp increase). However, based on the register values you provided, your hsw value is larger than your hbp value so this won't be possible. Instead, I’d try adjusting both hfp/hbp and vfp/vbp by 0.5 * hsw.

    Regards,

    Melissa

  • 0 in reply to melissaw
    TI__Expert 3500 points

    Hey guys, I work with Brad and happened across this.... so would this work? I THINK if you were to invert the HSYNC (bit 21 of RASTER_TIMING_2) and then possibly set the horizontal sync width to what would otherwise be your HTOTAL - HSYNC that you actually want, I think that provides the shape/control you want.  I don't have an EVM here to try this; but I'm pretty sure this would work.