Part Number: TMS320C6670
Recently, I am doing some sw developments on c66x platform. In my application, the following conditions are existent:
1/ L1D cache is enabled with size 32KB.
2/ the coprocessor, bcp and fftc are employed. Due to the memory pressure, the incomes or outcomes of these coprocessors should be located in the shared L2 memory or DDR3.
My question are:
1/ Since L1D cache is enabled, after packet-dma has finished the job and transferred the outcome into the shared L2 or DDR3 memory, Is the SW cache coherence operation, i.e. CACHE_wbL1d((shared L2 or DDR3 memory address), size, ...) necessary? So I suppose that the overall operations are:
Step 1) Enable L1D cache
Step 2) Start the packet-dma
Step 3) packet-dma finishs the data transfer
Step 4) CACHE_wbL1d((shared L2 or DDR3 memory address), size, ...)
2/ When to access the outcomes of coprocessor located in the shared L2 or DDR3 memory, Is CACHE_invL1d((shared L2 or DDR3 memory address), size, ...) necessary? So I suppose that the overall operations are:
Step 1) Enable L1D cache
Step 2) CACHE_invL1d((shared L2 or DDR3 memory address), size, ...)
Step3) read the outcomes of packet-dma
Thanks for your kind help!
