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TDA4VM: TDA4 LPDDR layout Problem

H-J
Intellectual 300 points

Part Number: TDA4VM

Hi TI Engineer

I see this requirement in "J7_LPDDR4_Layout_Guidelines":
T-Branch, single-ended impedance  35/70 ohm
T-branch, differential impedance  70/140 ohm
But it's very difficult for our Layout to do that now:140ohm（diff），70ohm（single）
(board thickness:2mm,16 layers)
We calculated the impedance according to the reference design layout(PROC078E7_BRD.brd)
T-Branch, single-ended impedance  about 28/50 ohm
T-branch, differential impedance  ：about 56/96 ohm
Can we adjust it to the following impedance in our design?
T-Branch, single-ended impedance  30/55 ohm
T-branch, differential impedance  ：60/100 ohm
Thanks very mach!
  • 0
    TI__Expert 6655 points

    Hi jian:

    You can follow LPDDR4 guide design it. (http://www.ti.com/lit/an/spracn9/spracn9.pdf)

    T-branch LPDDR_CA signal follow the routing requirements (2x impedance for branched segments).  Because too thin line can not manufacture. The impedance optimize to 3mils about 54 ohm and 8 mils about 33 ohm.

    TI has simulate the SI and test at EVM board. LPDDR4 speed match DM request.

    You can follow EVM board optimize it.

    Best Regards!

    Han Tao