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PRTCSS PWRCTRIO[2:0] Interrupts support help

Amir
Prodigy 50 points

Hello,

I am able to control the PRTCSS using the PRTCIF registers and control the GIO with no problems
I do not use the RTC.
I have read the PRTCSS guide and according to the PRTCSS PWRCTRIO[6:0] may be used as interrupt sources and
That the PRTCSS may generate only one interrupt to the DM365 via the PRTCIF.
So from that i understand that i must configure the PRTCSS/PRTCIF regs for interrupts  and when i get a PRTCSS  (irq 29)
interrupt read the PRTCSS interrupt status flag to see which GIO was the source.

I also saw in the ARM subsystem guide that there are 3 interrupt sources to the INTC (irqs: 56,57,58)  from the PRTCSS,
And that i must configure the interrupt mux register for them to work.
The GPIO guide only explains about GPIO sources 0 - 15 and doesnot say anything about PWRCTRIO[2:0],
Same for the PRTCSS guide, it only explains about the PRTCSS/PRTCIF combined single interrupt source.
How do i configure these Interrupts PWRCTRIO[2:0] ??
Should i configure the PRTCSS registers for these interrupts and the interrupt mux register and they will work 
With out any more configurations ?

Thanks you 

 

  • 0
    TI__Genius 9510 points

     The current document has missing information about GPIO Bank 6.  This will be corrected an made available in a few days.  But I've included the missing information (see attachment).

    ·         Interrupts can come in from PWRCTRIO[2:0] as GPIO PINS, they can use these 3 interrupts and they are mapped in the AINTC as int#56, #57, #58 as noted in the ARM INT Table for those pins when used as GPIOs from the PRTCSS perspective.  

    ·         To use them, these three PWRCTRIO[2:0] are mapped as GIO[106:104] in BANK6. The associated BANK6 registers need to be configured by setting bit 6 (EN6) of the BINTEN register and the GPIO BANK6 registers similar to other GPIO BANK 0-5 configuration.

     

      

     4338.GPIO_Bank_6.doc

  • 0 in reply to Marcus Cooksey
    TI__Mastermind 37786 points

    Marcus,

    My understanding is that if I want to use PWRCTRIO[2:0] as interrupt source (int# 56, 57, 67), we need to configure the GPIO register for GIO[106~104] as well.

    But there are registers for GPIO direction/interrupt status/interrupt for rising/failing edge in both PRTCSS registers and GPIO registers. Which one need we set? Or we need to set both for same value?

  • 0 in reply to Chris Meng
    Expert 2315 points

    I want to use PWCTRIO0 on my evmdm365 as wired to SW2 for user interaction.  How do I address offset addresses of GIO_DIR and GIO_IN and also maybe GIO_FALL_INT_EN etc in PRTCSS register? In other words, what is the address of PTRCSS that I add the Offsets to given in table 12 on page 32 of sprufj0a  ?

    Thanks, Jinh T.

  • 0 in reply to Jinh
    Expert 2150 points

    hi, Jinh T.

    i had a previous post here , maybe it can help you with the address.

    Mike.

  • 0 in reply to zanget
    Expert 2315 points

    Thanks Mike,

    where do I find code for davinci_rtcss_write() and davinci_rtcif_write()?  I am using dvsdk_02_10_01_18 on MV5 kernel.

  • 0 in reply to Jinh
    Expert 2150 points

    Hi, Jinh,

    I had re-write this functions cus I don’t want to use

    linux-2.6.32.17-psp03.01.01.38\drivers\rtc\ rtc-davinci.c

    (You can found it here actually):

     

    davinci_rtcss_write() and davinci_rtcif_write()

     

    This is what I had so far :

     

     

    static inline void davinci_rtcif_write(u32 val, u32 addr)

    {

         

          __raw_writel(val, IO_ADDRESS(0x01c69000) + addr);

    }

     

    static inline u32 davinci_rtcif_read(u32 addr)

    {

          return __raw_readl(IO_ADDRESS(0x01c69000) + addr);

    }

     

    static inline void davinci_rtcif_wait()

    {

        while (davinci_rtcif_read(DAVINCI_PRTCIF_CTLR) & DAVINCI_PRTCIF_CTLR_BUSY)

               cpu_relax();

    }

     

    static inline void davinci_rtcss_write(unsigned long val, u8 addr)

    {

          davinci_rtcif_wait();

     

          davinci_rtcif_write(DAVINCI_PRTCIF_CTLR_BENL_LSB | addr,

                         DAVINCI_PRTCIF_CTLR);

          davinci_rtcif_write(val, DAVINCI_PRTCIF_LDATA);

     

          davinci_rtcif_wait();

    }

     

    static inline u8 davinci_rtcss_read(u8 addr)

    {

          davinci_rtcif_wait();

     

          davinci_rtcif_write(DAVINCI_PRTCIF_CTLR_DIR |DAVINCI_PRTCIF_CTLR_BENL_LSB |addr, DAVINCI_PRTCIF_CTLR);

     

          davinci_rtcif_wait();

     

          return davinci_rtcif_read(DAVINCI_PRTCIF_LDATA);

    }

     

     also, there is another thread here.