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AM5718: About PCIE controller: Base Address Registers

user5011627
Intellectual 340 points

Part Number: AM5718

Hi,

I want to use the PCIE controller as end-point. I refer the technical reference manual and I have some questions. Can you tell me where can I find the initialization configuration for BAR0?

Table 24-695 shows that  according to ECAM Cfg Space/DIF CS/CS2, I can configure BAR0 through three registers. What is DIF CS/CS2 ? I didn't find any explanation for it.

Whether it's PCIECTRL_EP_PCIEWIRE_BAR0 or PCIECTRL_EP_DBICS_BAR0, I can see the explanation similar to the following picture. I want to know what's the difference between [19:4] and [31:20], except for the type of RW or R.

Thank you for your reply!

  • 0
    TI__Genius 17176 points

    See TRM Section "Double Mapping of the PCIe Local Control Registers" for an explanation of DIS CS/CS2.

    See TRM Section "Base Address Registers (BAR) Initialization" for details on BAR configuration, including the R vs RW portion of the BAR base address.  The number of read-only bits in the BAR base address is dependent on the programmed size of the BAR bask in register PCIECTRL_EP_DBICS2_BAR0_MASK.

    Also see TRM Section "PCIe Controller Low Level Programming Model" for the recommended init sequence.