• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 99 subscribers
  • Views 348 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

66AK2H06: SerDes PLL reference clock input

Koichiro Tashiro
Mastermind 22945 points

Part Number: 66AK2H06

Hi,

My customer made their own board with 66AK2H06.
On the board, customer observed over/undershoot/step at USBCLK and PCIECLK inputs.
Customer wants to remove them.
Please see attached excel sheet for waveforms. DDR3CLK, ARMCLK and SYSCLK are shown as comparison.
66AKH06_CLK.xlsx
Customer’s schematics are also attached in the excel sheet and they put AC coupling capacitors near 66AK2H06.
The capacitor value is 0.1uF, this is the same value as used on EVM.
Is this implementation correct?
Are there any other rules/guidelines customer needs to follow?

Thanks and regards,
Koichiro Tashiro

  • 0
    TI__Mastermind 46460 points

    Koichiro,

    The recommendations in the Hardware Design Guide will produce a robust implementation.  The LJCB buffer used for the DDR clock input contains the required termination and biasing so that serial capacitors are all that is needed.  The termination is 100 ohms differential.  It is always active.  The reference clock input to the SERDES blocks, USBCLK and PCIECLK, are not terminated until the software is loaded and the SERDES interface is initialized.  Therefore, the signal integrity will be poor until this initialization completes.  Once initialized, the SERDES will apply a 100-ohm differential termination which will minimize the clock signal reflections.  Therefore, same as the LJCB clock inputs, serial capacitors are all that is needed.

    Tom