Other Parts Discussed in Thread: AM4376
Hello expert team.
We have two development platforms based on the AM3351 and the AM4376 CPUs. Both platforms have a JEDEC compliant eMMC connected to the MMC interface of the CPU. Currently, we have some problems understanding the timing of the MMC bus and the behavior of the system.
For both platforms, the MMC bus is operating at 48 MHz with CPU@OPP100. The relevant timing parameters (obtained from data sheets) are as follows:
| PCB | |
| Signal delay: | 320 ps (approx.) |
| eMMC (JEDEC compliant) | |
| Minimum setup requirement: | 3 ns |
| Minimum hold requirement: | 3 ns |
| Output delay (min / max): | 2,5 ns / 13,7 ns |
| AM3351 | |
| Minimum setup requirement: | 4,1 ns |
| Minimum hold requirement: | 3,76 ns |
| Output delay in standard mode (min / max): | -4 ns / 14 ns |
| Output delay in high-speed-mode (min / max): | 3 ns / 14 ns |
| AM4376 | |
| Minimum setup requirement: | 4,1 ns |
| Minimum hold requirement: | 3,76 ns |
| Output delay in standard mode (min / max): | -7,4 ns / 4,4 ns |
| Output delay in high-speed-mode (min / max): | 0,8 ns / 7,4 ns |
Input timing
For the input timing, data is output and sampled on the rising edge of the clock signal. Because setup and hold requirements are equal for both CPU types, the setup and hold margins can be calculated as follows:
Setup margin: [MMC clock period] – [eMMC max. output delay] – [CPU hold requirement] – [2 x PCB signal delay] =
for AM3351/AM4376: 20,83 ns – 13,7 ns – 4,1 ns – 0,64 ns = 2,39 ns
Hold margin: [eMMC min. output delay] + [2 x PCB signal delay] =
for AM3351/AM4376: 2,5 ns + 0,64 ns = 3,14 ns
Output timing (standard mode)
In standard mode, the CPU changes data on the falling edge of a clock cycle. The eMMC samples data on the rising edge.
Setup margin: [MMC clock period / 2] – [CPU max. output delay] – [eMMC setup requirement] =
for AM3351: 10,415 ns – 14 ns – 3 ns = -6,515 ns
for AM4376: 10,415 ns – 4,4 ns – 3 ns = 3,015 ns
Hold margin: [MMC clock period / 2] + [CPU min. output delay] – [eMMC hold requirement] =
for AM3351: 10,415 ns + (-4 ns) – 3 ns = 3,415 ns
for AM4376: 10,415 ns + (-7,4 ns) – 3 ns = 0,015 ns
Output timing (high-speed mode)
In high-speed mode, the CPU changes data on the rising edge of a clock cycle. The eMMC samples data on the rising edge, too.
Setup margin: [MMC clock period] – [CPU max. output delay] – [eMMC setup requirement] =
for AM3351: 20,83 ns – 14 ns – 3 ns = 3,83 ns
for AM4376: 20,83 ns – 4,4 ns – 3 ns = 13,43 ns
Hold margin: [MMC clock period] + [CPU min. output delay] – [eMMC hold requirement] =
for AM3351: 3 ns – 3 ns = 0 ns
for AM4376: 0,8 – 3 ns = -2,2 ns
Conclusion
The input timing provides sufficient margin for both CPU platform.
The output timing depends on the mode of operation (setting of the HSPE bit): For the AM3351, only the high-speed mode (HSPE = 1) provides sufficient margin. For the AM4376, only the standard mode (HSPE = 0) provides sufficient margin.
Do you agree, with the timing analysis above and the final conclusion?
Surprisingly, the AM3351 also operates in standard mode without getting any access errors. We are very confused about that, because the setup requirement is violated. Do you have any idea, why?
Thank you in advance and best regards
Stefan
