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AM6548: DDR4 Maximum Frequency Configuration

Daisuke Maeda
Guru 20045 points
Part Number: AM6548

I checked the GEL file to configure DDR4 to 800MHz (DDR-1600) as the maximum frequency, but it seems to be configured to 400MHz (DDR-800).

\ti\ccs910\ccs\ccs_base\emulation\boards\am65x\gel\M4_Common\M4_PLL_Common.gel
//Set to 400 MHz
#define DDR_M_FRAC_MULT  0

//1600MT/s (800MHz DDR)
#define DDR_M_INT_MULT  320
#define DDR_N_DIV               10-1
#define DDR_SD_DIV            4  
#define DDR_M2_DIV            2

DDR_PLL_CLKOUT = DDR_CLKINP × ((DDR_M_INT_MULT + DDR_M_FRAC_MULT) / (DDR_N_DIV + 1)) × (1 / DDR_M2_DIV)
DDR_PLL_CLKOUT = 25.0MHz × ((320 + 0) / (9 + 1)) × (1 / 2) = 400MHz

Is my understanding correct?

Best regards,

Daisuke

  • 0
    Guru 20045 points

    Hi,

    Should the GEL file be changed as follows to configure DDR4 to 800MHz (DDR-1600) as the maximum frequency?

    \ti\ccs910\ccs\ccs_base\emulation\boards\am65x\gel\M4_Common\M4_PLL_Common.gel
    //Set to 400 MHz
    #define DDR_M_FRAC_MULT  0

    //1600MT/s (800MHz DDR)
    #define DDR_M_INT_MULT  640
    #define DDR_N_DIV               10-1
    #define DDR_SD_DIV            4 
    #define DDR_M2_DIV            2

    DDR_PLL_CLKOUT = DDR_CLKINP × ((DDR_M_INT_MULT + DDR_M_FRAC_MULT) / (DDR_N_DIV + 1)) × (1 / DDR_M2_DIV)
    DDR_PLL_CLKOUT = 25.0MHz × ((640 + 0) / (9 + 1)) × (1 / 2) = 800MHz

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    Guru 20045 points

    Hi,

    I checked to configure DDR4 to 800MHz (DDR-1600) as the maximum frequency by using CTT (Clock Tree Tool).

    Is my understanding correct?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 32585 points

    Hi,

    We are looking into this and reply as soon as possible.

    Best regards,
    Kevin

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 32585 points

    Hi,

    It is confirmed that the output of the PLL should be 1/4 the desired data rate. This is because the DDRSS adjusts the input clock to achieve the desired data rate. Thus, it is correct that the GEL is configuring the PLL to 400 MHz; however, this is the required frequency to result in a 1600 data rate.

    Best regards,

    Kevin

  • 0 in reply to Kevin S
    Guru 20045 points

    Hi Kevin-san,

    Thank you for your reply.

    The DDR_CKP/N maximum frequency is 800MHz (Cycle time = 1.25 ns).

    When the DDR_PLL_CLKOUT frequency is 400 MHz, the input clock is adjusted to 800 MHz and the DDR_CKP/N frequency is 800 MHz?

    Could you  tell me how to configure registers to adjust (multiply) the input clock by DDRSS?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 32585 points

    Hi,

    Yes, the PLL output should be 1/2 of the DDR cycle time (or, 1/4 the data rate). 

    >>Could you  tell me how to configure registers to adjust (multiply) the input clock by DDRSS?

    In general, you should not need to change any register to achieve this as software should already be configured to the max DDR4-1600 data rate. I will have to confirm internally, but I believe the multiply may not even be programmable inside the DDRSS. In summary, the GEL you referenced is already configured for DDR4-1600 and you do not need to change the clock settings. 

    Best regards,
    Kevin

  • 0 in reply to Kevin S
    Guru 20045 points

    Hi Kevin-san,

    Thank you for your reply.

    I confirmed that DDR_CKP/N frequency is 800 MHz and DDR_PLL_CLKOUT frequency is 400 MHz (the 1/2 divided version frequency from OBSCLK0 is 200 MHz) on TMDX654GPEVM with default GEL configuration.

    Best regards,

    Daisuke