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XDC Configuration - Entry Function - Misaligned from the mapped start-address

Vinoth
Intellectual 760 points

Hi,

To set the start address of the entry function (_c_int00) making use of Pkg.addExecutable module & linker cmd file.

It was working as expected in Cortex-A8 target.

 

 Pkg.addExecutable(PROGRAM_NAME, targ, targ.platform,{lopts: '-i ' + environment['xdc.root'] + '/packages' + ' -l link.cmd'}).addObjects(PROGRAM_SOURCES);

linker.cmd

    boot > 0x81000000

      {

      -l ti\targets\arm\rtsarm\lib\boot.aea8f<boot.oea8f>(.text)

      } 

Making use of the link.cmd file to map the entry function ( _c_int00) in the Cortex-M3 core.

For a surprise, i found the mapping address is misaligned.

SECTIONS 

{

    //EXTMEM_CORE1

    boot > 0x8d200000

      {

      -l   ti\targets\arm\rtsarm\lib\boot.aem3<boot.oem3>(.text)  

      } 

}

From the map file, finding _c_int00 map into 0x8d20_0000 + 1 

ENTRY POINT SYMBOL: "_c_int00"  address: 8d200001

& 

A constant __TI_static_base_ mapped into 0x8d20_0000

8d200000   __TI_static_base

 

-Vinoth

  • 0
    TI__Mastermind 30830 points

    The cortex M3 is a pure ARM Thumb2 machine.

    The least significant bit of all function pointers and vectors is set to '1' per Thumb2 requirements.

    Is this report an observation of something unexpected or is something misbehaving?

    Alan

  • 0 in reply to Alan DeMars
    TI__Intellectual 760 points

    Alan,

    Thanks for your clarification.

    On the DM814x platform, I build a sample application ( A8, M3 & DSP).

    I have to bring-up the target in NAND Boot mode.

    I don't find issue on creating the A8 binary image & booting from DDR.

    But facing issue with M3 binary image build.

    While i try to build the image & map to DDR section, finding the following three section maps to 0x0

     

    .resetVecs 

    *          0    00000000    0000003c     

                      00000000    0000003c     frameq_ti814x_vpssm3_xem3.oem3 (.resetVecs)

    .bootVecs 

    *          0    0000003c    00000008     NOLOAD SECTION

                      0000003c    00000008     boot.aem3 : boot.oem3 (.bootVecs)

    .ducatiGates 

    *          0    000007f0    00000010     UNINITIALIZED

                      000007f0    00000010     frameq_ti814x_vpssm3_xem3.oem3 (.ducatiGates)

    .vecs      0    00000800    00000140     

                      00000800    00000140     frameq_ti814x_vpssm3_xem3.oem3 (.vecs)

     

    I don't understand what the necessity of this sections. 

    Can move this section to DDR?

    & Copy back to 0x0 location on M3 start-up?

     

    Please advice me

     

    -Regards5466.map.txt