• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 388 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

66AK2G12: Interrupt Latency Time

Krishna Boopathy J
Intellectual 340 points
Part Number: 66AK2G12
Other Parts Discussed in Thread: SYSBIOS

Hi

I am booting TI-RTOS on the 66AK2G12 processor using the ARM core.

As a part of my requirement, I have a an interrupt coming from GPIO and inside the ISR, I am performing some sequence of R/W statements to access a memory through PCIe. 

I probed to determine the time taken by the processor to detect the interrupt and call the ISR and also the time taken to execute the ISR routine. During the probing session, I noticed that after booting the board and when the first interrupt occurs the processor takes some extra time to since the moment the interrupt occurs and till the time it enters the ISR routine.

But after several interrupt sequences the processor takes lesser time to detect the interrupt and to start executing the ISR routine. (During first run it takes 3.7 uS and after several interrupts the processor takes only about 1.9 to 2 uS to detect the interrupt occurrence and to start executing the ISR routine).

I would like to know if this is a common phenomena (or) does it have to do something with TI-RTOS? 
Also please give us data on the interrupt latency of the processor.

Does TI-RTOS has any control over the processor's interrupt handling time?

Thank you.

--Krishna

  • 0
    TI__Guru** 116770 points

    Krishna,

    For GPIO function and PCIE, are you using TI PRocessor SDK RTOS. I want to understand your setup before providing guidance on the expected interrupt latency.

    The TI RTOS latency for different ARM cores is provided here:

    bios_6_7x_xx_xx\packages\ti\sysbios\benchmarks\doc-files

    Generally, higher latency during the first run with lower number subsequently is caused due to performance when the cache is cold vs warm which is why you need to find average over multiple iterations to get an accurate number.

    TI RTOS is very light weight in operation and adds a very small latency to the the interrupt latency of the processor.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Intellectual 340 points

    Hi Rahul,

    Yes for GPIO and PCIE we are using the drivers provided by TI Processor SDK RTOS.

    Setup:

    --> On the K2G eval board, we are generating a GPIO interrupt to the processor from the I2C expander by toggling the SW14. We are probing the INT pin on the I2C_EXPANDER ic.
          Inside the ISR routine, first we make a GPIO pin(TP124 - GPIO0_71) high, Then we are executing some PCIE R/W instructions. Finally before exiting the ISR the GPIO pin(TP124 - GPIO0_71) is made low.

    We can find that the ISR routine takes almost constant time interval. 
    But the interrupt latency, the time from the INT pin going low to GPIO pin going high, is differing. For the first iterations its around 3.7 uSec. And subsequently its reduced during next several iterations. And then after few iterations, the interrupt latency settles to a constant value (1.8 uSec). (See attachment).

    So is this a normal phenomena. Is there any suggestion to reduce this effect. Because in our requirement its very critical for us to achieve a much lower interrupt latency time.

    With Regards,

    Krishna.