Part Number: AM4377
Other Parts Discussed in Thread: AMIC120
We are trying to get the GPMC Burst Mode working on the AM4377 to a FPGA. Following the setup detailed in AM437x and AMIC120 ARM® Cortex™-A9 Processors Technical Reference Manual (SPRUHL7H - January 2018), Section 9.1, we are not able to produce the same results as per Section 9.1.5.1.3 (GPMC Configuration for Synchronous Burst Read Access). We are using the same values as table 9-44.
The GPMC setup on the board works, but generates single reads and not burst reads as per Figure 9-45.
We are using TI-RTOS with PDK_AM437x_1_0_15, and the Startware framework.
The GPMC is setup as:
GPMC_DEVICETYPE_NORLIKE, /* devType */
GPMC_DEVICESIZE_16BITS, /* devSize */
GPMC_MUXADDDATA_ADMUX, /* addrDataMux */
In the File GPMC_V1.c, the requred config registers are set by the following functions as part of the GPMC_open_v1 function :
GPMCReadTypeSelect(hwAttrs->gpmcBaseAddr,
hwAttrs->chipSel,
GPMC_READTYPE_SYNC);
GPMCWriteTypeSelect(hwAttrs->gpmcBaseAddr,
hwAttrs->chipSel,
GPMC_WRITETYPE_SYNC);
GPMCAccessTypeSelect(hwAttrs->gpmcBaseAddr,
hwAttrs->chipSel,
GPMC_MODE_READ,
GPMC_ACCESSTYPE_MULTIPLE);
GPMCAccessTypeSelect(hwAttrs->gpmcBaseAddr,
hwAttrs->chipSel,
GPMC_MODE_WRITE,
GPMC_ACCESSTYPE_MULTIPLE);
GPMCDevPageLenSet(hwAttrs->gpmcBaseAddr,
hwAttrs->chipSel,
GPMC_DEV_PAGELENGTH_EIGHT);
These changes are built and the required library files are made and used. This is verified to work via changing values and checking the Registers in the debugger.
The call to read is as follows, and returns the correct data in tempRxBuffer:
GPMC_Transaction tempGPMC;
tempGPMC.transType = GPMC_TRANSACTION_TYPE_READ;
tempGPMC.txBuf = NULL;
tempGPMC.count = 8;
tempGPMC.arg = NULL;
tempGPMC.rxBuf = (void *)tempRxBuffer;
tempGPMC.offset = 0x0100;
if (GPMC_transfer(gpmcHandle, &tempGPMC) == true)
{
The GPMC is initialised with :
GPMC_init();
GPMC_Params gpmcParams;
GPMC_Params_init(&gpmcParams);
GPMC_socGetInitCfg(BOARD_GPMC_INSTANCE, &cfg);
gpmcHandle = GPMC_open(BOARD_GPMC_INSTANCE, &gpmcParams);
The GPMCTransfer function resolves to the function GPMC_nor_read_v1(GPMC_Handle handle, const GPMC_Transaction *transaction), which results in a pointer memory transfer.
while (size > 0)
{
if(hwAttrs->devSize == GPMC_DEVICESIZE_16BITS)
{
*pData16++ = *pAddr16++;
if (size == 1)
{
size = 0;
}
else
{
size --= 2;
}
}
}
Something says to me that this memory transfer can not result in a burst read, and some other command or method is required. But, in saying that, and using the setup in Section 9.1.5.1.3, and the Starterware API provides the driver, we would expect this to work within the GPMC core.
We must be missing something, but can't see what it is. Why does this force a single read and not a burst read as per the setup in Section 9.1.5.1.3? None of the examples with the framework use this method, and are of no help, so an example of a working method would also help.
Andy
