Hi,
High undershoot/overshoot coming on 100 MHz diff clock on PCI-Reference clock input connected to DSP. External AC coupled LVDS clock is given to this input.
Q1. H/W design says the input clock buffer for PCIECLKn/p are having internal termination of 100 ohm? Is there any setting to be done to enable this 100 ohm Res or it’ll be enabled by default?
Q2. Is the input buffer for PCIECLJn/p a CML buffer, In Datasheet it’s mentioned serdes/cml, pl. refer page 34 of HW design guide. What is serdes buffer? What will be the default setting for it, CML or serdes buffer?
Q3. HW design guide also says these serdes reference clocks are internally AC coupled. Pl. refer page 35. So do we need to put external AC cap, or LVDS clock at 3.3V can be directly connected.
One observation: if we put external Res of 100 ohm then the clocks are becoming fine. CML input buffers have the internal termination Res and biasing ckt. I doubt the PCICLKn/p to come-up in CML mode needs some settings to be done..?
