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TMS320C6748 EMIFA, UPP, McASP Questions

I have a question about the EMIFA.  It is not clear to me to disable the FLASH, SDRAM interfaces when using EMIFA.  I intend to use it for asynchronous accesses to the FPGA only, please let me know.

Is there a specific location that the interrupt routine entry point for the UPP has got to be attached?

I am a little confused about this register (sprugj5b  UPP Users Guide, pg 37).  This is how I am interpreting it:

TXSIZEx: the amount of data that must be in the tx Fifo before the UPP starts to send the data out.

RDSIZEx: The amount of data that the DMA controller reads from memory when the transmit fifo indicates it is ready for data.

In this interpretation, this register is not used for UPP receive?  Please let me know the proper use of this register.

Lastly, I am planning to use the McASP to transfer data out of the DSP (after processing).  I will be transferring at least 307 Mbits/Sec, using multiple lanes (between 6 to 8). Due to the nature of the data, I would like to use TDM mode with the Tx FIFO (the McASP will not be receiving data).  As the data may be bursty, I would need the DMA engine for the McASP to only get data when data is available, not when the buffer is empty.  Can you suggest a way to do this without involving the CPU?  It appears to me that if the McASP issues a DMA request, the DMA engine will get data whether the data is there or not.

Thank you.