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CCS/TMDSEVM572X: Problem with DPLL lock.

Anton Khrenkov
Prodigy 230 points

Part Number: TMDSEVM572X

Tool/software: Code Composer Studio

Hello!
I have a problem.
Some times ago I use code with no problems, but now this code is not working.
I use pcie_sample.c to tune pcie controller.
The problem appear when I try to tune DPLL.
I call pcieSerdesCfg(void) from pcie_sample.c which call PlatformPCIESS1PllConfig(void) from pcie_sample_board.c.
Function PlatformPCIESS1PllConfig(void) configure PLL.
Function sticks when it checks DPLL lock status.
It read bit #0 in CM_IDLEST_DPLL_PCIE_REF register (shift from base:0x0000 0104, address:0x4A00 8204).
If DPLL is locked this bit must be 0x1, but its value 0x0 (In bypass mode or in stop mode).
Bits 1:3 in this register is 0x0 (As I understand, this told me that DPLL is in transient state).
Bit 4 in this register is 0x1 (DPLL has been init).

Before I check DPLL lock state I exec this code:

uint32_t regVal;   

/*OCP2SCP_SYSCONFIG[1] Soft Reset*/
regVal = HW_RD_REG32(SOC_OCP2SCP3_BASE + 0x10U) & 0xFFFFFFFDU;

regVal |= 0x02U;

HW_WR_REG32(SOC_OCP2SCP3_BASE + 0x10U, regVal);

/*OCP2SCP_SYSSTATUS[0] Reset Done*/
while ((HW_RD_REG32(SOC_OCP2SCP3_BASE + 0x14U) & 0x01U) != 0x01U)
{
	;
}

/*OCP2SCP_TIMING[9:7] Division Ratio = 1*/
regVal = HW_RD_REG32(SOC_OCP2SCP3_BASE + 0x18U) & 0xFFFFFC7FU;

regVal |= (uint32_t) 0x8U << 4U;

HW_WR_REG32(SOC_OCP2SCP3_BASE + 0x18U, regVal);

/*OCP2SCP_TIMING[3:0] (SYNC2) = 0xF*/
regVal = HW_RD_REG32(SOC_OCP2SCP3_BASE + 0x18U) & 0xFFFFFFF0U;

regVal |= 0xFU;

HW_WR_REG32(SOC_OCP2SCP3_BASE + 0x18U, regVal);


/*PCIe DPLL - M&N programming; CLKSEL*/
regVal = HW_RD_REG32(SOC_CKGEN_CM_CORE_BASE + CM_CLKSEL_DPLL_PCIE_REF);

HW_SET_FIELD(regVal, CM_CLKSEL_DPLL_PCIE_REF_DPLL_DIV, 0x09U);

HW_SET_FIELD(regVal, CM_CLKSEL_DPLL_PCIE_REF_DPLL_MULT, 0x2EEU);

HW_WR_REG32(SOC_CKGEN_CM_CORE_BASE + CM_CLKSEL_DPLL_PCIE_REF, regVal);

/*SigmaDelta SD DIV programming */
HW_WR_FIELD32(SOC_CKGEN_CM_CORE_BASE + CM_CLKSEL_DPLL_PCIE_REF,
			  CM_CLKSEL_DPLL_PCIE_REF_DPLL_SD_DIV, 0x06U);

/*PCIe DPLL - M2 programming*/
HW_WR_FIELD32(SOC_CKGEN_CM_CORE_BASE + CM_DIV_M2_DPLL_PCIE_REF,
			  CM_DIV_M2_DPLL_PCIE_REF_DIVHS, 0x0FU);

/*DPLL Enable*/
HW_WR_FIELD32(SOC_CKGEN_CM_CORE_BASE + CM_CLKMODE_DPLL_PCIE_REF,
			  CM_CLKMODE_DPLL_PCIE_REF_DPLL_EN,
			  CM_CLKMODE_DPLL_PCIE_REF_DPLL_EN_DPLL_LOCK_MODE);

Give me advice, please. Why DPLL is not locked. What I must do to get locked DPLL.

  • 0
    TI__Genius 17176 points

    Do you know what has changed in the setup since it last worked?

    Do you have access to probe the clkout1 or clkout2 pins on your board?  If so, can you configure the output of the PCIe DPLL to appear on one of these pins for observation?  Details on how to do this are provided in TRM section "CM_CORE_AON_CLKOUTMUX Overview".  The clock you want to observe is called PCIE_M2_CLK.  If the DPLL fails to lock, it should fall back to Bypass mode.  This will allow us to determine the frequency of the clock coming into the DPLL and see if there is an issue with the clock coming in.

    Can you also load your register configuration into the Clock Tree Tool to confirm that the PCIe DPLL is programmed to receive a 20MHz clock input?

    Finally, can you check what is programmed in the DPLL_SELFREQDCO field of the CM_CLKSEL_DPLL_PCIE_REF register?  You can try changing the the value of this bit to see if that has an effect in your system.

  • 0 in reply to B.C.
    Prodigy 230 points

    B.C., thanks for your answer!

    B.C. said:
    Do you know what has changed in the setup since it last worked?

    Last time when I change code, this peace of program working as well. First I successful configure pcie and set connection between evm and my board with FPGA. After this I start configure DMA but stop working and return to configure now, after 2-3 months.

    B.C. said:
    Do you have access to probe the clkout1 or clkout2 pins on your board?  If so, can you configure the output of the PCIe DPLL to appear on one of these pins for observation?  Details on how to do this are provided in TRM section "CM_CORE_AON_CLKOUTMUX Overview".  The clock you want to observe is called PCIE_M2_CLK.  If the DPLL fails to lock, it should fall back to Bypass mode.  This will allow us to determine the frequency of the clock coming into the DPLL and see if there is an issue with the clock coming in.

    I configure the output of the PCIe DPLL to appear on clkout1. I used P7 ball.

    // Select clkout1 on P7
// CTRL_CORE_PAD_GPMC_CLK
HW_WR_FIELD32_RAW(0x4A0034C0, 0xF, 0x0, 0x2);

// Enable CLKOUTMUX1_CLK
// CM_COREAON_CLKOUTMUX1_CLKCTRL
HW_WR_FIELD32_RAW(0x4A0086A0, 0x100, 0x08, 0x01);

// Selects divided version of PCIE_M2_CLK
// CM_CLKSEL_CLKOUTMUX1
regVal = 0x11U;
HW_WR_REG32(0x4AE0615C, regVal);

    Afref this I probe signal on P16 connector, pin #35. I saw signal 20MHz. Also I saw SYS_CLK1 and SYS_CLK2 (changing value in CM_CLKSEL_CLKOUTMUX1 register). I saw 20MHz too.

    B.C. said:
    Can you also load your register configuration into the Clock Tree Tool to confirm that the PCIe DPLL is programmed to receive a 20MHz clock input?

    I load my register configuration in Clock Tree Tool. DPLL_PCIE_REF receive 20MHz. If I set DPLL_PCIE_REF mode to "LOCKED" in output is 100MHz. If I set DPLL_PCIE_REF mode to "LOW_POWER_PYPASS" in output is 20MHz.

    B.C. said:
    Finally, can you check what is programmed in the DPLL_SELFREQDCO field of the CM_CLKSEL_DPLL_PCIE_REF register?  You can try changing the the value of this bit to see if that has an effect in your system.

    Changing DPLL_SELFREQDCO field unfortunately has no effect.

    Also probe P19 connector, pin #58-59 (PCI_CONN_REFN, PCI_CONN_REFP), and I saw 100MHz signal.

    What is the next step of diagnostic should be? Unfortunately, I have no idea...

  • 0 in reply to Anton Khrenkov
    TI__Genius 17176 points

    That is great progress!  Thanks for checking all of those items.  The clock input to the DPLL looks good, and the CTT shows that the DPLL is correctly configured to output 100MHz.

    Do you have another board or device that you could try, to see if the issue follows the device?

    Regarding the 100MHz that you see on the pins, I assume that the system is designed to use an external 100MHz clock from an onboard clock generator.  Let me know if you disagree.  Regardless, the DPLL is still required to be locked at 100MHz for the system to operate.

  • 0 in reply to B.C.
    Prodigy 230 points

    Hello, B.C.!

    B.C. said:
    Do you have another board or device that you could try, to see if the issue follows the device?

    Yes, I found another board and run my code on it. It works fine! So, the problem is in my board, not in my code.

    Do I have a chance to find the problem and fix it?

    B.C. said:
    Regarding the 100MHz that you see on the pins, I assume that the system is designed to use an external 100MHz clock from an onboard clock generator.  Let me know if you disagree.  Regardless, the DPLL is still required to be locked at 100MHz for the system to operate.

    Yes, you are right. I configure system to get 100Mhz (N = 9, M = 150, M2 = 15, DPLL_SELFREQDCO = 0).

  • 0 in reply to Anton Khrenkov
    TI__Guru 56837 points

    Anton,

    Can you please submit a request to return the EVM via this link:

    http://www.ti.com/support-quality/additional-information/customer-returns.html

    Regards,

    Kyle