OMAP-L138: DDR2 Dual-Memory Configuration

Hi, Wenbo,

The OMAP-L138 LSDK uses K4T1G164QF-BCE7 DDR-2 chip which is 64Mx16 (1GB) memory. I'll check internally to see if dual-memory of different size can be supported. 

Rex

Thank you Rex.

We were able to use a 128Mx16 (2Gb) DDR2 device, but we wanted to expand the DDR2 size to 4Gb. The OMAP-L138 DDR2 controller document sprugj4b stated that 512MByte (4Gb) is supported with a x16bit device. Is a dual-memory configuration with two 256Mbyte DDR2 devices with x8bit data width each (one device connects to D0-7 on DDR2 data bus, another connects to D8-15 on DDR2 data bus) identical to the above mentioned single-memory configuration with one 512Mbyte device (128Mx16bit)?

Can you please let me know?

Thanks,

Wenbo   

There seemed a conflict in TI documents in a few places regarding the maximum DDR2 memory size that OMAP-L138 can support. The DDR2 controller document sprugj4b stated 512Mbytes in section 3 paragraph "This section presents an example describing how to interface the DDR2 memory controller to a DDR2/mDDR-400 512-Mbyte device.", but the datasheet SPRS586J stated 256M DDR2 memory spacing (0xC000 0000 0xCFFF FFFF 256M DDR2/mDDR Data) in the memory map Table 3-4. Can you please clarify the maximum DDR2 memory size that OMAP-L138 can support, 256Mbytes, or 512Mbytes?

Do you or anyone from TI know the answer?

Thanks,

Wenbo

Hi Wenbo

The SPRUGJ4b is a very old doc. I would recommend using the unified TRM

http://www.ti.com/lit/ug/spruh77c/spruh77c.pdf

from this , we have removed the 512 Mbytes in the DDR chapter.

The datasheet also highlights that DDR memory map supports 256 MBytes only.

So you will not be able to get to 512 Mbytes with any configuration.

Hope this clarifies.

Regards

Mukul 

Wenbo

Our messages crossed.

So as you noticed and I confirmed in my previous post, OMAPL138 does not support having a 512 MBytes DDR memory space. This is comprehended in the latest documentation (datasheet and TRM)

Hope this helps.

Regards

Mukul 

Thank you very much Mukul. This really helps. I have another question regarding the EMIFA external memories on the OMAP-L138.

The datasheet SPRS586J stated an external 512M SDRAM on EMIFA (EMA_CS0) in the memory map Table 3-4 .Could we use both the EMIFA SDRAM and DDR2 SDRAM in our design at the same time? Is there any conflict or issues?

Would the EMIFA of OMAP-L138 be able to support up to four devices, an NOR flash, an NAND flash, an SDRAM and an FPGA on the EMIFA bus?

Best regards,

Wenbo

Hi Wenbo 

Over the years I have seen this query come up for EMIFA, but not sure if any customer has got something this complex with 4 loads on EMIFA. 

We do put a note in the datasheet to highlight things that customer should do , if they are planning to go this route

EMIFA SDRAM Loading Limitations

EMIFA supports SDRAM up to 100 MHz with up to two SDRAM or asynchronous memory loads. Additional loads will limit the SDRAM operation to lower speeds and the maximum speed should be confirmed by board simulation using IBIS models

There are no other known functional issues going down this route. You will likely see degradation in max clock as well as "simultaneous" access to EMIFA as the end point , if you were trying to read/write simultaneously from EMIFA SDRAM/FPGA/NOR or NAND flash. 

We do not have any throughput /concurrency data with all 4-5 chip selects being accessed concurrently etc. 

Regards

Mukul 

Thanks a lot Mukul.

The EMIFA SDRAM must be an SDR (Single Data Rate) SDRAM. Correct?

Best regards,

Wenbo

Hi Wenbo

That is correct. EMIFA only supports SDR SDRAM - it does not support DDR2 or LPDDR1.

Regards

Mukul 

Hi Mukul,

If multiple devices are connecting on the EMIFA bus (NOR flash, NAND flash, FPGA and SDRAM), the OMAP datasheet does not mention any termination recommendation to the data bus of EMIFA interface. I think it's easy to place termination resistors for the address lines close to the OMAP processor, but for the data lines, do we need the termination resistors for each device, and if so, should they be placed close to the device not the OMAP? Not sure if T has any layout guideline document for the EMIFA? Thank you.

Wenbo

Hi Wenbo,

We don't have any guidance for combining that many devices on the EMIFA bus. The address/command termination close to the SoC should sufficient but the data bus will be more problematic. I suggest that you simulate your layout to ensure that the data bus is stable at all the devices for both read and write.  I have seen a tree connection for data bus with a center terminating resistor at the point where the bus separates and connects to each device but that was with connections to only two devices. 

Regards, Bill

Thanks very much. I hope someone from TI can help with the following timing question on EMA interface of OMAP-L138.

Currently, we have four device loads on the EMIFA bus (NOR flash, NAND flash, FPGA and SDRAM). This slows down the rising edge and falling edge of clock and data of EMA interface. Therefore we encountered a timing issue. We changed the EMA_Clock speed from maximum of 100MHz to a lower frequency say 50MHz, this helped the set-up time, but the hold-up time still failed. We minimized the clock delay to help the hold up time by routing the clock trace as short as possible, and we had to introduce additional delays to the other EMA signals that originally failed hold-up time to make it pass. All this is done by hardware, either by layout or additional hardware way to adjust the timing.

I am wondering, is there any configuration in OMAP-L138 that can be used by software so that we can introduce certain amount of delay or wait to the EMA signals so that the timing requirement can be met? In other words, is there a software way to adjust the timing of EMA for SDRAM synchronous device to meet the timing requirement? My understanding is that if the wait/delay is going to be a multiple of clock cycles, that would not help the hold-up time, but if the wait or delay can be set/adjusted to a fraction of a clock cycle, that would be helpful. Is it possible to do it by software? Does the OMAP-L138 have such feature on EMA interface?

Thanks,

Wenbo

Wenbo,

It appears from your implementation that you are trying to stretch the functionality of the OMAP-L138 beyond its reasonable memory capabilities.  There is limited support for this old device.  Have you considered a newer device that has more memory bandwidth and supports a larger amount of memory?  Are you using both the ARM core and the DSP core in the OMAP-L138?

Tom

Thank you Tom. We will use OMAP-L138 as we want to reuse the software developed in previous design. Yes, we use both ARM and DSP core.

I am looking for a software way to adjust the timing for EMIFA interface to meet the timing requirements. I think the set-up time or hold-up time is programmable, isn't it? Does TI have any reference doc for the EMIFA interface for timing or EMIFA software development guide?

Thanks,

Wenbo

Hi Wenbo,

The setup and hold times are programmable for the asynchronous connections to the FPGA and NOR memories but the same does not exist in the registers for the SDRAM interface.  Are you attempting to change the timing for one of the memories other than the SDRAM?

Regards, Bill