Dear TI team,
I have been checking our DDRs specs, and they are able to work with Spread Spectrum clock, I have been checking also the TDA2P TRM and I didn't see anything clear about if it is possible to enable this feature in the TDA EMIF controller. Because we are facing some issues related to the clock of the DDR 666MHz. Could you clarify this topic? Do you have other tips? (Of course we have already checked the layout).
Thanks and regards!
Dear Kyle,
Yes of course, the problem is, that we saw a peak at 666MHz over the limit in our compliance measurements, and we have been searching where is the problem, and it seems the problem is in the CLK/#CLK node near our DDR modules, where we have a termination to these signals:
Thats why we are searching now how we can solve this issue, we are working to perform DDR simulations, maybe the impedance of this traces is not good matched, but also we are talking with the DDR supplier in order to know which is the best way to apply the termination to their DDR3 modules.
Then, as far as I understand, there is no way from the TDA side, to try to investigate this problem. Do you have any recommendation?
Thanks and best regards!
