Part Number: AM3352
Other Parts Discussed in Thread: TPS65217
I see from a previous conversation with TI rep that "The AM335x IOs are not fail-safe, so no external potential should be applied to an IO until the associated power supply is valid. Any external potential being applied to an IO before it is powered is considered an EOS." I am using PMIC TPS65217D. Some of our devices fail I am checking the fail-safe violation condition. I see GPIO 1_19 , connected to VLDO4 of TPS65217 comes up to 2.2V 20 µs before I make its pull up to another 3.3 Vrail high. So here the external potential applied (3.3V rail) is 20 µs after GPIO high. But then the complete high to 3.3Vrail happens 1.76s after VLDO4 high. Will that be a potential fail safe violation. I am asking because of the intermediate high value on GPIO of 2.34V. I can share scope shot here.
PS: I was directed to post it here based on TI Case CS0169621
