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Hot boot failure

2 to 3 % of time, boot fails as per below on custom board a 60deg:

   Kernel release : Linux 2.6.33-rc4

    Kernel version : #36 PREEMPT Mon Jan 3 16:42:04 CET 2011

 

 Mounting /proc             : [SUCCESS]

 Mounting /sys              : [SUCCESS]

 Mounting /dev              : [SUCCESS]

 Mounting /dev/pts          : [SUCCESS]

 Populating /dev            : [SUCCESS]

 Mounting /var              : [SUCCESS]

 Load FPGA                  : [SUCCESS]

 Starting eeprom init       : eth0: attached PHY driver [Generic PHY] (mii_bus:phy_addr=1:00, id=1410e70)

[SUCCESS]

 Starting eeprom update     : [SUCCESS]

 Starting tuner             : [SUCCESS]

 Starting Dibcom            : [SUCCESS]

 Starting temp sensor       : [SUCCESS]

 Starting syslogd           : [SUCCESS]

 Starting bftpd             : [SUCCESS]

 Starting telnetd           : [SUCCESS]

 Starting webserver         : [SUCCESS]

 Starting uart_xml_manage   : [SUCCESS]

 Starting LED               : [SUCCESS]

 Starting FPGA              : [SUCCESS]

 

System initialization complete.

 

Please press Enter to activate this console. JFFS2 notice: (401) read_dnode: node CRC failed on dnode at 0x3bd228: read 0xffffffff, calculated 0x2cf9866e

PHY: 1:00 - Link is Up - 100/Full

uart_xml_manage: :275: ‚1àå40 Assertion `‡¡Žç

' failed.

ipv6: module has no symbols (stripped?)

WebServer: :275: ‚1àå40 Assertion `‡¡Žç

' failed.

manage_dibcom_chip: 4@ƒà‚!„à0’å:275: : Assertion `' failed.

 

 

 

 

when file system is changed from jffs2 to cramfs :

 

 

 

   Kernel release : Linux 2.6.33-rc4

    Kernel version : #40 PREEMPT Tue Jan 11 14:19:01 CET 2011

 

 Mounting /proc             : [SUCCESS]

 Mounting /sys              : [SUCCESS]

 Mounting /dev              : [SUCCESS]

 Mounting /dev/pts          : [SUCCESS]

 Populating /dev            : [SUCCESS]

 Mounting /var              : [SUCCESS]

 Load FPGA                  : [SUCCESS]

 Starting eeprom init       : Error -3 while decompressing!

c03265bd(2740)->c165c000(4096)

Error -3 while decompressing!

c03285bd(2740)->c165c000(4096)

Bus error

[FAILED]

 Starting FPGA              : [SUCCESS]

 Starting eeprom update     : [SUCCESS]

 Starting tuner             : [SUCCESS]

 Starting Dibcom            : [SUCCESS]

 Starting temp sensor       : [SUCCESS]

 Starting syslogd           : Error -3 while decompressing!

c03285bd(2740)->c165c000(4096)

Error -3 while decompressing!

c03245bd(2740)->c165c000(4096)

[SUCCESS]

 Starting bftpd             : Error -3 while decompressing!

c03285bd(2740)->c165c000(4096)

Error -3 while decompressing!

c03285bd(2740)->c165c000(4096)

Error -3 while decompressing!

c03285bd(2740)->c165c000(4096)

Error -3 while decompressing!

c03245bd(2740)->c165c000(4096)

Bus error

[FAILED]

 Starting telnetd           : [SUCCESS]

 Starting webserver         : [SUCCESS]

 Starting uart_xml_manage   : [SUCCESS]

Error -3 while decompressing!

c03245bd(2740)->c165c000(4096)

Error -3 while decompressing!

c03285bd(2740)->c165c000(4096)

DSPLINK Module (1.65.00.02) created on Date: Nov 23 2010 Time: 17:37:45

 Starting DSP               : [SUCCESS]

 Starting LED               : [SUCCESS]

 

System initialization complete.

 

Please press Enter to activate this console. Error -3 while decompressing!

c03245bd(2740)->c165c000(4096)

Error -3 while decompressing!

c03285bd(2740)->c165c000(4096)

ipv6: module has no symbols (stripped?)

^C

Please press Enter to activate this console.

 

 

 

We're suspecting flash SPI or DDR2 read/write corruption.

and we're looking for help to check the DDR2 config

 

we're using this as a reference

http://processors.wiki.ti.com/index.php/Programming_mDDR/DDR2_EMIF_on_OMAP-L1x/C674x mDDR_DDR2_Memory_Controller_Register_Calc_Rev4.xls

the interesting fields we found, but still looking for guidance on what to tweek where:

IBANK_POS, DDRDRIVE1, BOOTUNLOCK, DDRDRIVE0, TIMING_UNLOCK, LPMODEN, MCLKSTOP_EN, SR_PD, T_ODT, EXT_STRBEN, PWRDNEN.

  • If you believe it is a DDR timing issue, then try maxing out all the timing registers. The following is from the EVM GEL file which maxes out the DDR timings:

    DRPYC1R  |=  0x7;
    EMIFDDR_SDTIMR1 = (0x7F << 25)             |  // tRFC
                            (0x07 << 22)             |  // tRP
                            (0x07 << 19)             |  // tRCD
                            (0x07 << 16)             |  // tWR
                            (0x1F << 11)             |  // tRAS
                            (0x1F << 6)              |  // tRC
                            (0x07 << 3)              |  // tRRD
                            (EMIFDDR_SDTIMR1 & 0x4)  |  // Reserved
                            (0x03 << 0);                // tWTR

    EMIFDDR_SDTIMR2 = (EMIFDDR_SDTIMR2 & 0x80000000)                       |  // Reserved
                            (((unsigned int) ((70000 / 7812.5) - 0.5))  << 27)   |  // tRASMAX
                            (0x3                                        << 25)   |  // tXP
                            (0x0                                        << 23)   |  // tODT (Not supported)
                            (0x7F                                       << 16)   |  // tXSNR
                            (0xFF                                       << 8)    |  // tXSRD
                            (0x07                                       << 5)    |  // tRTP (1 Cycle)
                            (0x1F                                       << 0);      // tCKE

    Jeff

    Jeff