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AM6526: AM65x R5F memory access time (TCM and MSMC)

Part Number: AM6526

Dear Sir,

What's the memory access cycle (access time) from R5F to TCM and MSMC respectively on AM65x? 

Will there be significant difference? 

BR, Rich

  • Hello Rich,

    see this thread for my analysis of R5f memory access latency:

    >> This leaves us with ~34 cycles for accesing MCU SRAM, ~104 cycles for accessing MSMC SRAM and ~146 cycles for accessing DDR RAM

    These numbers were eventually confirmed by TI.

    For TCM the access time is "1", as in zero latency, single cycle per access.

    Regards,

    Dominic

  • Hi 

    I find the topic and i have some problems about these

    Our team used csl_test(dmTimer_funcTest.c)  to do memory write with two different linker_r5.lds.

    Through CSL_armR5PmuReadCntr(0x1F) to calculate the memory read/write time 

    temp1 = CSL_armR5PmuReadCntr(0x1F);
    tmpdata = rwdata;
    temp2 = CSL_armR5PmuReadCntr(0x1F);
    temp1 = temp2 - temp1;
    if (temp1 > max_read)
        max_read = temp1;
    if (temp1 < min_read)
        min_read = temp1;
    avg_read = (avg_read * count + temp1) / (count+1);

    and used the different lds file to test "avg_read "

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/dmTimer_5F00_funcTest.7z

    MSMC3 <=> MCU0_R5F_TCMB0 

    But the "time"look no different

    Is our method has problem ?

    OR could you supply us TI's measure method ?

    thank you

  • Hi,

    I believe your approach has several issues:

    • You're trying to measure the time for performing a single assignment. My guess is that this is easily dominated by the overhead of the measurement. For my own tests I wrote/read "large" arrays of memory (256K if possible, smaller for the TCMs).
    • Your variables aren't declared volatile. If you're using the Release build (debug build wouldn't make sense for performance measurements) there's a chance that the compiler is optimizing your assignments. I checked the disassembly to make sure that the generated code actually measured the accesses I'm interested in.
    • By default your memory is mapped cacheable, so after the first access I'd expect the MSMC location to be just as fast as TCM.

    All of these could be the reason why you're seeing no difference, but most likely there'll be more than one factor rendering your measurements invalid.

    Unfortunately I can't share our code (I'm not TI).

    Regards,

    Dominic

  • Hi TI Champs:

    The original Poster is our customer.

    I agree what Rath mentioned about here.

    Please comment if the Rath's comment is correct.

    If no, do we have the other measurement sample code to guide this customer?

    THanks.

    BR Rio

  • All, Yes I agree w/ the comments above, especially the results in the linked thread are from Jian in TI.  Fundamentally, to get to MSMC requires several hops (+latency) across the system interconnect to reach the MSMC memory, whereas TCM is "tightly coupled memory" to the R5F and is equivalent performance to hitting in the I$/D$ cache (single cycle access).

    Regards,

    Kyle