For the last few years we have made about 30 processor boards using the TMS320C6713BZDP running at 200MHz. We use an FPGA to perform block reads of data through the HPI. However, the last batch of 10 boards did not work in our system. I traced the problem to the HPI read.
FPGA uses HPI signals to read and write to HPI registers. So to do a block read, it does the following sequence.
Write start address to HPIA
Read from HPID auto increment mode
Repeat Read for HPID auto increment mode
Until final two reads from HPID in fixed mode (as per silicon errata document)
The FPGA takes care of the signal timing and monitors the HRDY signal.
This code has worked for years across all our boards with version 2.0 DSPs.
The last batch however will sometimes get the read from the first address wrong. It returns the contents of the address 6 words beyond the last word in the block.
So if want to read N words from address P then sometimes I will get the contents of P+N+6 as the first word. Rest of the words are OK.
This happens about 1 in 100 block reads so is fairly predictable.
I eventually worked out that the HPI read buffer was not getting cleared by the write to HPIA register as in SPRU578C 4.2.2 and data was left over from previous block read.
To fix this I added in a dummy read of the HPID in fixed mode before writing to the HPIA in the sequence above.
Now, the block reads work without problems.
Has the operation of the DSP changed or is there a subtle change to the latest version 2.0 chips?
Is this user's problem related to mine?
http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/p/32049/111570.aspx#111570
