Part Number: TDA4VM
Hi Ti,
I have several questions for TDA4 processor.
q1) for each CSI channel, can I use (2+1+1 Lane) or (2+2 Lane) configuration ?
q2) I searched the datasheet but each CSI channel has only 1 csi clock for the channel.
if I use 2+2 lane, how can I use the different clock for each 2 lane ?
q3) if (2+2 Lane) configuration is possible, into each 2 lane, images of different resolution and hz come in,
can TDA4 store each image to DRAM ? and does user use image cropping inside ?
Thanks,