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PROCESSOR-SDK-DRA8X-TDA4X: PCIe controller 3 is missing from Linux device tree for TDA4EVM

Uros Zivkovic
Intellectual 830 points

Part Number: PROCESSOR-SDK-DRA8X-TDA4X

Hello, we are analyzing Processor SDK Linux Automotive with goal of using it for software development for TDA4 SoC based platform.

Looking at TDA4 documentation we see the SoC have four PCIe controllers, we downloaded Processor SDK Linux Automotive to run some tests for those controllers and we noticed that PCIE3 controller is not included in Linux device tree for TDA4EVM.

We are wondering why is this the case, and how we can add it without causing any issues?

Regards.

Uros

  • 0
    TI__Intellectual 1385 points

    Hi Uros,

    Please find patch to enable PCIe3. TDA4EVM has only 3 PCIe instances brought out, that's why didn't add the 4th PCIe instance.

    From 2c8b246e9d3651deb3bcd24d9e68dfd68c574307 Mon Sep 17 00:00:00 2001
From: Kishon Vijay Abraham I <kishon@ti.com>
Date: Thu, 9 Apr 2020 07:23:45 +0530
Subject: [PATCH] Enabled PCIe3

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 .../dts/ti/k3-j721e-common-proc-board.dts     | 18 +++++-
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi     | 55 ++++++++++++++++++-
 arch/arm64/boot/dts/ti/k3-j721e.dtsi          |  3 +-
 3 files changed, 71 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 0bc4805ecfb2..2bcdca0a472d 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -672,7 +672,7 @@
 	idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
 		      <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
 		      <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
-		      <SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
+		      <SERDES3_LANE0_PCIE3_LANE0>, <SERDES3_LANE1_PCIE3_LANE1>,
 		      <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
 };
 
@@ -684,11 +684,11 @@
 };
 
 &serdes3 {
-	serdes3_usb_link: link@0 {
+	serdes3_pcie_link: link@0 {
 		reg = <0>;
 		cdns,num-lanes = <2>;
 		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_USB3>;
+		cdns,phy-type = <PHY_TYPE_PCIE>;
 		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
 	};
 };
@@ -699,12 +699,14 @@
 	ti,vbus-divider;
 };
 
+/*
 &usb0 {
 	dr_mode = "otg";
 	maximum-speed = "super-speed";
 	phys = <&serdes3_usb_link>;
 	phy-names = "cdns3,usb3-phy";
 };
+*/
 
 &usbss1 {
 	pinctrl-names = "default";
@@ -798,6 +800,11 @@
 	num-lanes = <2>;
 };
 
+&pcie3 {
+	pci-mode = <PCI_MODE_RC>;
+	num-lanes = <2>;
+};
+
 &pcie0_rc {
 	reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
 	phys = <&serdes0_pcie_link>;
@@ -816,6 +823,11 @@
 	phy-names = "pcie_phy";
 };
 
+&pcie3_rc {
+	phys = <&serdes3_pcie_link>;
+	phy-names = "pcie_phy";
+};
+
 &tscadc0 {
 	adc {
 		ti,adc-channels = <0 1 2 3 4 5 6 7>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 4e04d5b14521..17dfc76b8a8e 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -43,6 +43,11 @@
 			reg = <0x00004078 0x4>;
 		};
 
+		pcie3_ctrl: pcie-ctrl@407c {
+			compatible = "syscon";
+			reg = <0x0000407c 0x4>;
+		};
+
 		serdes_ln_ctrl: serdes_ln_ctrl@4080 {
 			compatible = "mmio-mux";
 			#mux-control-cells = <1>;
@@ -1096,7 +1101,7 @@
 			reg = <0x00 0x0e000000 0x00 0x00800000>,
 			      <0x44 0x00000000 0x00 0x00001000>;
 			reg-names = "reg", "cfg";
-			msi-map = <0x0 &gic_its 0x10000 0x10000>;
+			msi-map = <0x0 &gic_its 0x20000 0x10000>;
 			iommu-map = <0x0 &smmu0 0x08000 0x1000>;
 			dma-coherent;
 			ranges = <0x01000000 0x00 0x00001000  0x44 0x00001000  0x0 0x0010000>,
@@ -1115,6 +1120,54 @@
 		};
 	};
 
+	pcie3: pcie@2930000 {
+		compatible = "ti,j721e-pcie";
+		reg = <0x00 0x02930000 0x00 0x1000>,
+		      <0x00 0x02937000 0x00 0x400>,
+		      <0x00 0x02935000 0x00 0x400>;
+		reg-names = "intd_cfg", "user_cfg", "vmap";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
+		max-link-speed = <3>;
+		num-lanes = <2>;
+		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 242 1>;
+		clock-names = "fck";
+
+		pcie3_rc: pcie@e800000 {
+			compatible = "ti,j721e-cdns-pcie-host";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			bus-range = <0x0 0xf>;
+			cdns,max-outbound-regions = <16>;
+			cdns,no-bar-match-nbits = <64>;
+			vendor-id = /bits/ 16 <0x104c>;
+			device-id = /bits/ 16 <0xb00d>;
+			reg = <0x00 0x0e800000 0x00 0x00800000>,
+			      <0x44 0x10000000 0x00 0x00001000>;
+			reg-names = "reg", "cfg";
+			msi-map = <0x0 &gic_its 0x30000 0x10000>;
+			iommu-map = <0x0 &smmu0 0x0c000 0x1000>;
+			dma-coherent;
+			ranges = <0x01000000 0x00 0x00001000  0x44 0x10001000  0x0 0x0010000>,
+				 <0x02000000 0x00 0x00011000  0x44 0x10011000  0x0 0x7fef000>;
+		};
+
+		pcie3_ep: pcie-ep@e800000 {
+			compatible = "ti,j721e-cdns-pcie-ep";
+			reg = <0x00 0x0e800000 0x00 0x00800000>,
+			      <0x44 0x10000000 0x00 0x08000000>;
+			reg-names = "reg", "addr_space";
+			cdns,max-outbound-regions = <16>;
+			max-functions = /bits/ 8 <6>;
+			max-virtual-functions = /bits/ 8 <0x4 0x4 0x4 0x4 0x0 0x0>;
+			dma-coherent;
+		};
+	};
+
 	main_uart0: serial@2800000 {
 		compatible = "ti,j721e-uart", "ti,am654-uart";
 		reg = <0x00 0x02800000 0x00 0x100>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index 279d17689139..eaa64e1d7144 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -143,10 +143,11 @@
 			 <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
 			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
 			 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
-			 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/
+			 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x02000000>, /* PCIe Core*/
 			 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
 			 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
 			 <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
+			 <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
 			 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
 			 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
 			 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
-- 
2.17.1