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TDA4VM: Ethernet switch CPSW-9G and CPSW-2G configurations

Hiren Vora
Intellectual 260 points
Part Number: TDA4VM

Hi TI Team,

We are working on TDA4 based our hardware and we have specific questions on CPSW-2G and CPSW-9G Eth Switch. Please provide the response the following queries.

Q1 What are the default CPSW-9G switch PORT settings when TDA4 software is loaded ? i.e. RGMII, RMII, GMII 
Please provide the source path of the software where this configuration  are located.
Q2 In our hardware design - we have connected external  SoC to PORT 2 of CPSW-9G via RGMII interface,  do we need to change register settings on TDA4 software SDK 06.02.00 to make link up and running with external device ? 
If the answer is yes, where do we need to do changes in software  to PORT 2 work for external device for RGMII interface.
Q3 Please help to clarify the following doubts, 
 Working SET UP: Our connection to MCU_RGMII1 PORT <--> External PHY <--> RJ45 connector <--> PC or ethernet device                
- MCU_RGMII1 PORT on CPSW-2G is connected to MCU R5 core, but we are able to communicate from Linux on A72 core to PC (via RJ45). 
Doubt: Is there any internal communication between MCU R5 and Linux A72 ? IF it is yes, what is the underneath communication interface ? 
  • 0
    TI__Expert 8935 points

    Hi Hiren,

    -Q1-

    The default port settings are:

    • RGMII: MAC ports 0, 2, 3 and 7
    • QSGMII: MAC ports 1, 4, 5 and 6

    It's a board-related configuration, so it's handled by the CPSW LLD's board utils (<PDK>/packages/ti/drv/cpsw/examples/cpsw_apputils/V1/cpsw_appboardutils_j721e_evm.c). The pinmux configuration is taken care by PDK's board library (<PDK>/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c).

    That being said, from the CPSW9G point of view, the port isn't configured by the underlying driver unless the application opens the port. In this context, application means EthFw or a CPSW9G driver example. In Processor SDK 6.2 release, the EthFw running on Main R5F core 0 opens only ports 2 and 3 (due to resource partitioning reasons).

    -Q2-

    Is that a MAC-to-MAC type of connection with the external SoC? Software changes would have to be done in the CPSW LLD's utils and PDK board library paths that I mentioned in previous Q1. For MAC-to-MAC, you could use the helper function CpswAppUtils_setNoPhyCfgRgmii().

    -Q3-

    CPSW2G is in the MCU domain, but any core in the SoC can access it. So, MCU R5 or A72 could use it in a given configuration. Linux running on A72 has a native driver for CPSW2G.