We have a system based on the 5505A DSP. We are using a 32 Khz clock crystal into the RTC of the DSP. Our code initializes the theSYSCLK to 100 Mhz. At power on the DSP boots and the resulting SYSCLK is 12 mhz. Pulling the reset pin low at this point, the DSP reboots and SYSCLK is now 100 Mhz.
At power on reset sequence, reading back the registers immediately after the initialization is complete shows that the PLL registers failed to update with the new values. The values assigned during ROM Boot are the values that are read. After a hardware reset (after a power on reset sequence), the PLL registers have the new programmed values.
I also noticed that TESTLOCKMON bit is asserted by the time it is read for the first time.
Here is the initialization code:
void USB_initPLL(void)
{
Uint16 timeout;
timeout = CSL_USB_PLL_TIMEOUT;
/* bypass PLL */
CSL_FINST(sysCtrlRegs->CCR2, SYS_CCR2_SYSCLKSEL, BYPASS);
/* Configure the PLL for 100 MHz */
sysCtrlRegs->CGICR = 0x8000;
sysCtrlRegs->CGOCR = 0x0000;
sysCtrlRegs->CGCR2 = 0x0806;
sysCtrlRegs->CGCR1 = 0x8BE8;
/* Busy wait until TESTLOCKMON is high or timeout */
while(!((sysCtrlRegs->CGCR2) & (0x08)))
{
timeout--;
if(timeout == 0)
{
break;
}
}
/* Switch to PLL clk */
CSL_FINST(sysCtrlRegs->CCR2, SYS_CCR2_SYSCLKSEL, LOCK);
}
