• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 98 subscribers
  • Views 1570 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4VM: Issue in generating SD bootable image by multicoreimageGen

Fan_Zhang
Expert 4260 points
Part Number: TDA4VM

Hi, Export,

My customer is asking for a demo to boot more cores by SBL. As I didn't find a demo target for this requirement that I am trying to generate one. (If there is any, please help to point out). My test step is as follow.

1. build ipc_spi demo

make -s ipc_spi_master_demo_app BOARD=j721e_evm SOC=j721e BUILD_PROFILE=release CORE=mcu1_0 BUILD_OS_TYPE=tirtos

make -s ipc_spi_slave_demo_app BOARD=j721e_evm SOC=j721e BUILD_PROFILE=release CORE=mpu1_0 BUILD_OS_TYPE=tirtos

2. boot through CCS, connect to mcu1_0, load master.xer5f, connect to mpu1_0, load slave.xa72fg, run and log shows the sample application completes successfully.

3. generate multicoreimage

copy master.rprc and slave.rprc to (SDK_INSTALL_PATH)/pdk/packages/ti/boot/sbl/tools/multicoreImageGen/bin folder

cd /(SDK_INSTALL_PATH)/pdk/packages/ti/boot/sbl/tools/multicoreImageGen/bin

./MulticoreImageGen LE 55 app 4 master.rprc 0 slave.rprc

4. copy the generated app file into SD

5. boot from SD card and get below log

SBL Revision: 01.00.09.02 (Apr 9 2020 - 11:50:05)
SYSFW ver: 19.8.0-v2019.08 (Terrific Llama

It seems tiboot3.bin and sysfw.bin work well but SBL cannot parse the multicore image.

Please help to check if anything wrong in above steps.

Thanks a lot.

  • 0
    TI__Guru* 77774 points

    Hi,

    You can look at the sbl example application to get a multicore image which boots different cores.

    Use the following commands to build all the applications:

    cd <PATH_TO_SDK>/pdk/packages/ti/build

make sbl_boot_test -sj CORE=mpu1_0
make sbl_boot_test -sj CORE=mpu1_1
make sbl_boot_test -sj CORE=mcu1_0
make sbl_boot_test -sj CORE=mcu1_1
make sbl_boot_test -sj CORE=mcu2_0
make sbl_boot_test -sj CORE=mcu2_1
make sbl_boot_test -sj CORE=mcu3_0
make sbl_boot_test -sj CORE=mcu3_1

    Now stitch all these images together:

    cd <SDK_PATH>/psdk_rtos_auto_j7_06_02_00_21/pdk/packages/ti/boot/sbl/example/k3MulticoreApp/binary/j721e

../../../../tools/multicoreImageGen/bin/MulticoreImageGen LE 55 app 0 sbl_baremetal_boot_test_j721e_evm_mpu1_0TestApp_release.rprc 1 sbl_baremetal_boot_test_j721e_evm_mpu1_1TestApp_release.rprc 4 sbl_baremetal_boot_test_j721e_evm_mcu1_0TestApp_release.rprc 5 sbl_baremetal_boot_test_j721e_evm_mcu1_1TestApp_release.rprc 6 sbl_baremetal_boot_test_j721e_evm_mcu2_0TestApp_release.rprc 7 sbl_baremetal_boot_test_j721e_evm_mcu2_1TestApp_release.rprc 8 sbl_baremetal_boot_test_j721e_evm_mcu3_0TestApp_release.rprc 9 sbl_baremetal_boot_test_j721e_evm_mcu3_1TestApp_release.rprc

    This will create the app which will load 8 core, the output would look something like:

    SBL Revision: 01.00.09.02 (Apr 10 2020 - 04:03:37)
SYSFW  ver: 19.12.1-v
                     19.12a (Terrific Lla
MPU1_0 running
MPU1_1 running
MCU1_1 running
MCU2_0 running
MCU2_1 running
MCU3_0 running
MCU3_1 running
MCU1_0 running
MCU1_0 reports: All tests have passed

    The ipc spi example is meant to be run using the CCS + GELs as there is a dependency that the slave application needs to start before the master. The standalone applications too will not run when using the SBL.

    Regards,

    Karan

  • 0 in reply to Karan Saxena
    TI__Expert 4260 points

    Hi, Karan,

    Thanks very much! This demo is indeed what I am looking for.

    As you explained, in ipc spi example the slave(MPU1_0) needs to start before the master(MCU1_0). Based on my understanding of the boot order in SBL, it will boot all other cores, and at last boot the core running SBL, which is MCU1_0. This boot order guarantees slave starts before master. Why the generated multicore image failed to boot MPU1_0 and MCU1_0.

    Thanks.

  • 0 in reply to Fan_Zhang
    TI__Guru* 77774 points

    Hi,

    Glad to help you there. Please click on Verify answer if that was what you were looking for.

    Your understanding is correct, the slave will indeed start before the master, I didn't realise that this won't be a problem here.

    The failure of the combined application when loading from SBL is not because the multicore image formation is incorrect. The standalone appimage of the master and the slave too will not boot via the SBL. This is because for an application to run from the SBL the memory map should be compatible with the memory map of the SBL. The ipc_spi_master_demo_app and the ipc_spi_slave_demo_app were never tested with SBL.

    CCS has a different way of loading and hence running the xer5f and xa72fg will work.

    We can probably address the SBL loading the application in the next release.

    Regards,

    Karan

  • 0 in reply to Karan Saxena
    TI__Expert 4260 points

    Hi, Karan,

    Thanks for the explanation of ipc spi combined application failure.

    Is there any detailed documents regarding generating combined image for multi cores? Such as .lds file modification, items should be paid attention to, etc.. I think this is useful for customers to avoid various issues.

    Thanks. 

  • 0 in reply to Fan_Zhang
    TI__Guru* 77774 points

    Hi Felix,

    You can look at the http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_Foundational_Components.html for SBL related documentation, this will help you design you application to run from SBL. Once your standalone applications run from SBL, just take care that they do not have an overlaping memory map and then the combined appimage should be able to run from SBL.

    So two things need to be taken care in the .lds -

    1. It is such that the application runs from SBL.
    2. Two linker files should not have overlaping sections.

    I can probably come back when we have a document stating the specific information which addresses this aspect.

    Regards,

    Karan

  • 0 in reply to Karan Saxena
    TI__Expert 4260 points

    Hi, Karan,

    Got it.

    Thank you very much!