AM3354: GPMC questions

Hi,

Let me try to answer your questions.

Question 1: Can the Destination Address mode of CONST be used?  

When you say destination address mode is CONST, are you referring to configuration of the DMA? This mode is typically used when writing to a register (like McASP) where data is retrieved from the regiseter and transmitted from the device.
When the GPMC is in NOR mode, there is an address mapping from the the data space for that GPMC to a physical address that is sent to the NOR device. For example you would access address 0x0 of the NOR at CS0 by accessing the GPMC base address from the ARM core.
If you use a CONST destination address, the same address will be written to over and over.
Perhaps something like an FPGA can ignore the address and input data that way.

Question 2 - Can both GPMC devices use DMA?
The DMA can be used with NOR and NAND devices, but in different ways.
The NOR flash will break the DMA burst into several smaller GPMC accesses - depending on the GPMC config registers. Each write/read cycle might consist of address followed by one data or with readmultiple/writemultiple set the can burst upto 16 words per access, repeating until the DMA is completed. Typically the address will increase for each GPMC cycle.

The NAND flash operates differently with GPMC - it is not memory mapped. All addresses, commands, and data are written directly to GPMC_NAND_COMMAND_n , GPMC_NAND_ADDRESS_n , GPMC_NAND_DATA_n registers. To support DMA, the NAND uses a FIFO called the Prefetch/Write-Posting engine. The DMA can be used to fill or empty this FIFO when it is close to getting full or empty (FIFOTHRESHOLD).

Refer to SPRUH73Q 7.1.2.3.12.4 Prefetch and Write-Posting Engine

Good questions. What NAND device do you have?

-Mark