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CSL GPTimer code for 5504.

Mushtaq Syed56993
Intellectual 750 points

Hi:

I modified the GP Timer code in CSL for my application. It works fine for Timer 0; however, it doesn't work for Timer 1 or Timer 2(GPT). When I use it for Timer 0, I get interrupts; however, if I switch to Timer 1 or Timer 2, I don't get interrupts. I am enabling the global interrupts and IER0 has a value of 0x0010 indicating that the timer aggregate interrupt is enabled. The way I am modifying the code to switch from one timer to another is by changing GPT_0 to GPT_1 or GPT_2. Seems to me that is the only change to make. Could you please help?

Thanks a lot.

Cheers,

Mushtaq

  • 0
    Expert 2615 points

    Hi

    Are you not able to see even a single interrupt for GPT 1 and 2?. Changing the GPT instance to GPT_1 or GPT_2 should at least generate one interrupt. You need to clear the timer interrupt aggregation flag register(TIAFR) in the ISR to get the continuous interrupts from timer. TIAFR bits will be specific to the timer number.

    You need to change the ISR code in the CSL example to CSL_SYSCTRL_REGS->TIAFR = 0x01 << (timer nubmer); where as timer number is 0, 1 or 2.

    Pratap.

  • 0 in reply to Pratap Reddy M V
    Intellectual 750 points

    Hi Pratap:

    Yes, I am not getting a single interrupt with Timer1 and Timer2. This is what I am doing in the ISR.

    IRQ_clear(TINT_EVENT)

    CSL_SYSCTRL_REGS->TIAFR = 0x04 //for timer 2.

    For different timers I am changing the value loaded into TIAFR to clear the interrupt.

    Thanks a lot.

    Cheers,

    Mushtaq

  • 0 in reply to Pratap Reddy M V
    Intellectual 750 points

    Hi Pratap:

    The CSL code does not work for Timers 1 and 2 on the C5505 EVM. It works fine for Timer0. For Timer1 I used GPT_1 and CSL_SYSCTRL_REGS->TIAFR = 0x02 while for Timer2 I used GPT_2 and CSL_SYSCTRL_REGS->TIAFR = 0x04. For bot of them it hangs at the last line below. Could you please look into this?

    Thanks a lot.

    Cheers,

    Mushtaq

    CSL GPT TESTS!

    TIMER COUNT READ TEST!
    GPT Open Successful
    GPT Reset Successful
    GPT Config Successful
    GPT Count-1 Successful
    GPT Count-2 Success
    GTP Time Count Compare Successful
    GPT Stop Successful
    GPT Close Successful
    TIMER COUNT READ TEST PASSED!!


    TIMER COUNT RATE VERIFICATION TEST!
    THIS TEST VERIFIES WHETHER THE TIMER IS RUNNING AT CONFIGURED RATE OR NOT

    CPU clock is running at 100007KHz
    Timer Prescaler Divide Value is Set to Divide by 4
    GPT Runs at Rate 1/4 of the CPU System Clock
    GPT Count is Initialized to 1/4 of CPU Clock Cycles per Millisecond
    With Reference to CPU Clock GPT Will Take 1 Millisecond to Count Down the Timer to 0
    So The CPU Should Execute Approximately 100007(±1%) Clock Cycles From the Starting of the Timer Till the Expiry of the Timer

    GPT Open Successful
    GPT Reset Successful
    GPT Config Successful

  • 0 in reply to Mushtaq Syed56993
    TI__Expert 8065 points

    In order to receive TimerN (N = 0, 1, 2) interrupt, the correspond bit in TIAFR resister must be cleared. Try to clear the TIAFR register and see if you receive the interrupt you want. 

  • 0 in reply to Peter Chung
    Intellectual 780 points

    Hi,

    We're seeing the same problem with Timer1 and Timer2 on the EzDSP5535 board. Was there ever a resolution to this problem?

    Thanks,

    Jim

  • 0 in reply to james conway
    Prodigy 150 points

    Hi , 

    it seems that when doing reset (GPT_reset), we must have following values for IAFR reset:
    #define CSL_IAFR_TIMER_FLAG_0_RESETVAL (0x0001u)
    /** IAFR flag for GPT 1 */
    #define CSL_IAFR_TIMER_FLAG_1_RESETVAL (0x0003u)  /* instead of 0x0002u) */
    /** IAFR flag for GPT 2 */
    #define CSL_IAFR_TIMER_FLAG_2_RESETVAL (0x0005u) /* instead of 0x0004u) */
    That means always clear the first bit (IAFR GPT_0 flag).
    I don't know why .. Any idea ?
    Nicolas