Hi,
Is there any WatchDog reset to replace the manual reset by push button on board?
Or some HW registers can be triggered as SOC hard-reset?
br,
Ks.
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Hi,
Is there any WatchDog reset to replace the manual reset by push button on board?
Or some HW registers can be triggered as SOC hard-reset?
br,
Ks.
Hi Ks,
The WDG hardware cannot reset the SoC when WDG expires, instead a pin of the SoC can be asserted. It's expected that an external entity (such as PMIC) will monitor this pin and reset the SoC when pin is driven low.
Please refer to the http://downloads.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/mcusw/mcal_drv/docs/drv_docs/ug_wdg_top.html#ug_wdg_functional_dep_esm and http://downloads.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/mcusw/mcal_drv/docs/drv_docs/ug_wdg_top.html#ug_wdg_functional_top for details.
Watchdog design doc - http://downloads.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/mcusw/mcal_drv/docs/drv_docs/design_wdg_top.html
Regards,
Karan