AM5728: SPI buffer for long signal traces

Sudarshan,

The LVCMOS IOs for the SPI interfacer can drive a trace that long.  The question is whether you will meet the data sheet timing (setup/hold for the remote component on writes, and for our SoC on reads).   Any additional buffer will only add propagation delay making the situation worse.

You should compare the data sheets of the two devices and consider prop delays for your PCB traces to determine the max frequency that can be supported on your PCB.

Regards,

Kyle

Kyle,

The above question was raised because we had a previous issue w.r.t Inconsistent SPI Read using AM5728 when we had connected 3 SPI Slave devices on the SPI Bus. The SPI Bus was operated less than 5MHz and even then we had the failures. Hence i was not sure in any way we could take care of this issue.

Regards,

Sudarshan

Sudarshan,

In the case of a multi-point interface, reflections can lead to signal integrity issues that can cause functional fails.  You should run IBIS simulations of your PCB topology to validate that clocks and data signals look good at each endpoint.  You need to be especially careful that clock signals are monotonic at each endpoint.

Regards,

Kyle