Hi,
When I switch ethernet to 1Gbps, log shows below, but can't send or receive any packet.
[ 908.679337] cpsw 48484000.ethernet eth1: Link is Down
[ 910.690381] cpsw 48484000.ethernet eth1: Link is Up - 1Gbps/Full - flow control rx/tx
My network circuit like below:
* sorry for my terrible drawing...
As picture shows, TDA2Px use RGMII1 and MDIO to connect phy chip: 88E1512. And single from RGMII1_RXC and RGMII1_RXD0 shows below:
* 1000Mbps speed.
Since my oscilloscope detecting pens' bandwith is lower than 500Mhz, RGMII1_RXC shows like sin wave. But as I only series resistance between TDA2px and 88E1512, this wave actually should be square wave.
*100Mbps speed
And RGMII1_TXC and RGMII1_TXD0 has similar wave. So I think RGMII1 works fine.
And I read similar question: http://e2e.ti.com/support/processors/f/791/t/759078?Linux-AM3359-Ethernet-PHY-1Gbps-not-working
And dump DPLL shows clock is already enabled with 250MHz. And WR_RGMII_CTL register setting alright. Please refer my attachment.
I'm really clueless now. Would you please give me some suggestions?
Thanks a lot!
root@dra7xx-evm:~# omapconf show dpll
OMAPCONF (rev v1.73-17-g578778b built Tue Jun 12 01:50:26 IST 2018)
HW Platform:
Generic DRA74X (Flattened Device Tree)
DRA76X ES1.0 GP Device (STANDARD performance (1.0GHz))
Error: I2C Read failed
Error: I2C Read failed
Error: I2C Read failed
UNKNOWN POWER IC
SW Build Details:
Build:
Version: _____ _____ _ _
Kernel:
Version: 4.4.84
Author: ckt1010@ubuntu
Toolchain: gcc version 5.3.1 20160113 (Linaro GCC 5.3-2016.02)
Type: #2 SMP PREEMPT
Date: Tue Feb 25 11:26:52 CST 2020
|---------------------------------------------------------|
| DPLL Configuration | DPLL_USB | DPLL_PCIE_REF |
|---------------------------------------------------------|
| Status | Locked | Locked |
| | | |
| Mode | Lock | Lock |
| Automatic Control | Auto LPST | Auto LPST |
| LPST = Low-Power STop | | |
| FRST = Fast-Relock STop | | |
| LPBP = Low-Power ByPass | | |
| FRBP = Fast-Relock ByPass | | |
| MNBP = MN ByPass | | |
| | | |
| Sigma-Delta Divider | 4 | 4 |
| SELFREQDCO | 0 | 0 |
| | | |
| Ref. Frequency (MHz) | 20.000 | 20.000 |
| M Multiplier Factor | 480 | 75 |
| N Divider Factor | 9 | 0 |
| Lock Frequency (MHz) | 960 | 1500 |
| | | |
| CLKOUT Output | | |
| Status | Enabled | Gated |
| Clock Divider | 2 (x2) | 15 (x2) |
| Clock Speed (MHz) | 480 | 100 |
| | | |
| CLK_DCO_LDO Output | | |
| Status | Enabled | N/A |
| Clock Speed (MHz) | 960 | |
| | | |
| CLKOUTX2_M2_LDO Output | | |
| Status | N/A | Enabled |
| Clock Speed (MHz) | | 100 |
| | | |
|---------------------------------------------------------|
|-----------------------------------------------------------------------------------------------|
| DPLL Configuration | DPLL_MPU | DPLL_IVA | DPLL_CORE | DPLL_PER | DPLL_ABE |
|-----------------------------------------------------------------------------------------------|
| Status | Locked | Stopped | Locked | Locked | Locked |
| | | | | | |
| Mode | Lock | Lock | Lock | Lock | Lock |
| Automatic Control | Auto LPST | Auto LPST | Auto LPST | Auto LPST | Auto LPST |
| LPST = Low-Power STop | | | | | |
| FRST = Fast-Relock STop | | | | | |
| LPBP = Low-Power ByPass | | | | | |
| FRBP = Fast-Relock ByPass | | | | | |
| MNBP = MN ByPass | | | | | |
| Low-Power Mode | Disabled | Disabled | Disabled | Disabled | Disabled |
| | | | | | |
| Automatic Recalibration | Disabled | Disabled | Disabled | Disabled | Disabled |
| Clock Ramping during Relock | Disabled | Disabled | Disabled | Disabled | Disabled |
| Ramping Rate (x REFCLK(s)) | 2 | 2 | 2 | 2 | 2 |
| Ramping Levels | No Ramp | No Ramp | No Ramp | No Ramp | No Ramp |
| | | | | | |
| Bypass Clock | CLKINPULOW | CLKINP | CLKINP | CLKINP | CLKINPULOW |
| Bypass Clock Divider | 1 | 1 | | | |
| REGM4XEN Mode | Disabled | Disabled | Disabled | Disabled | Disabled |
| Duty Cycle Correction (DCC) | Disabled | Disabled | Disabled | Disabled | Disabled |
| | | | | | |
| Ref. Frequency (MHz) | 20.000 | 20.000 | 20.000 | 20.000 | 22.579 |
| M Multiplier Factor | 500 | 266 | 266 | 96 | 8 |
| N Divider Factor | 9 | 4 | 4 | 4 | 0 |
| Lock Frequency (MHz) | 2000 | 2128 (2128) | 2128 | 768 | 361 |
| | | | | | |
| M2 Output | | | | | |
| Status | Enabled | Gated | Gated | Gated | Enabled |
| Clock Divider | 1 (x2) | 2 (x2) | 2 (x2) | 4 (x2) | 1 (x2) |
| Clock Speed (MHz) | 1000 | 0 (532) | 532 | 96 | 180 |
| | | | | | |
| X2_M2 Output | | | | | |
| Status | | | | Enabled | Enabled |
| Clock Divider | | | | 4 | 1 |
| Clock Speed (MHz) | | | | 192 | 361 |
| | | | | | |
| X2_M3 Output | | | | | |
| Status | | Gated | Gated | Gated | Gated |
| Clock Divider | | 1 | 1 | 1 | 2 |
| Clock Speed (MHz) | | 0 (2128) | 2128 | 768 | 180 |
| | | | | | |
| H11 Output | | | | | |
| Status | | | Gated | Gated | |
| Clock Divider | | | 1 | 3 | |
| Clock Speed (MHz) | | | 2128 | 768 | |
| | | | | | |
| H12 Output | | | | | |
| Status | | | Enabled | Enabled | |
| Clock Divider | | | 4 | 4 | |
| Clock Speed (MHz) | | | 532 | 192 | |
| | | | | | |
| H13 Output | | | | | |
| Status | | | Enabled | Enabled | |
| Clock Divider | | | 62 | 8 | |
| Clock Speed (MHz) | | | 34 | 96 | |
| | | | | | |
| H14 Output | | | | | |
| Status | | | Gated | Gated | |
| Clock Divider | | | 5 | 2 | |
| Clock Speed (MHz) | | | 2128 | 768 | |
| | | | | | |
| H21 Output | | | | | |
| Status | | | Gated | | |
| Clock Divider | | | 6 | | |
| Clock Speed (MHz) | | | 2128 | | |
| | | | | | |
| H22 Output | | | | | |
| Status | | | Enabled | | |
| Clock Divider | | | 5 | | |
| Clock Speed (MHz) | | | 425 | | |
| | | | | | |
| H23 Output | | | | | |
| Status | | | Enabled | | |
| Clock Divider | | | 4 | | |
| Clock Speed (MHz) | | | 532 | | |
| | | | | | |
| H24 Output | | | | | |
| Status | | | Gated | | |
| Clock Divider | | | 6 | | |
| Clock Speed (MHz) | | | 2128 | | |
|-----------------------------------------------------------------------------------------------|
|----------------------------------------------------------------------------------------------|
| DPLL Configuration | DPLL_EVE | DPLL_DSP | DPLL_GMAC | DPLL_GPU | DPLL_DDR |
|----------------------------------------------------------------------------------------------|
| Status | Bypassed | Locked | Locked | Locked | Locked |
| | | | | | |
| Mode | LPBP | Lock | Lock | Lock | Lock |
| Automatic Control | Auto LPST | Disabled | Auto LPST | Auto LPST | Auto LPST |
| LPST = Low-Power STop | | | | | |
| FRST = Fast-Relock STop | | | | | |
| LPBP = Low-Power ByPass | | | | | |
| FRBP = Fast-Relock ByPass | | | | | |
| MNBP = MN ByPass | | | | | |
| Low-Power Mode | Disabled | Disabled | Disabled | Disabled | Disabled |
| | | | | | |
| Automatic Recalibration | Disabled | Disabled | Disabled | Disabled | Disabled |
| Clock Ramping during Relock | Disabled | Disabled | Disabled | Disabled | Disabled |
| Ramping Rate (x REFCLK(s)) | 2 | 2 | 2 | 2 | 2 |
| Ramping Levels | No Ramp | No Ramp | No Ramp | No Ramp | No Ramp |
| | | | | | |
| Bypass Clock | CLKINP | CLKINP | CLKINP | CLKINP | CLKINP |
| Bypass Clock Divider | 1 | 1 | | | |
| REGM4XEN Mode | Disabled | Disabled | Disabled | Disabled | Disabled |
| Duty Cycle Correction (DCC) | Disabled | Disabled | Disabled | Disabled | Disabled |
| | | | | | |
| Ref. Frequency (MHz) | 20.000 | 20.000 | 20.000 | 20.000 | 20.000 |
| M Multiplier Factor | 0 | 85 | 250 | 266 | 333 |
| N Divider Factor | 0 | 1 | 4 | 4 | 4 |
| Lock Frequency (MHz) | 0 (0) | 1700 | 2000 | 2128 | 2664 |
| | | | | | |
| M2 Output | | | | | |
| Status | Enabled | Gated | Enabled | Enabled | Enabled |
| Clock Divider | 1 (x2) | 1 (x2) | 4 (x2) | 2 (x2) | 2 (x2) |
| Clock Speed (MHz) | 20 (20) | 850 | 250 | 532 | 666 |
| | | | | | |
| X2_M2 Output | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| X2_M3 Output | | | | | |
| Status | Gated | Gated | Gated | Gated | Gated |
| Clock Divider | 1 | 4 | 10 | 1 | 1 |
| Clock Speed (MHz) | 0 (0) | 425 | 200 | 2128 | 2664 |
| | | | | | |
| H11 Output | | | | | |
| Status | | | Enabled | | Enabled |
| Clock Divider | | | 40 | | 8 |
| Clock Speed (MHz) | | | 50 | | 333 |
| | | | | | |
| H12 Output | | | | | |
| Status | | | Enabled | | |
| Clock Divider | | | 8 | | |
| Clock Speed (MHz) | | | 250 | | |
| | | | | | |
| H13 Output | | | | | |
| Status | | | Gated | | |
| Clock Divider | | | 10 | | |
| Clock Speed (MHz) | | | 2000 | | |
| | | | | | |
| H14 Output | | | | | |
| Status | | | Enabled | | |
| Clock Divider | | | 24 | | |
| Clock Speed (MHz) | | | 83 | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | |
|----------------------------------------------------------------------------------------------|
root@dra7xx-evm:~# omapconf read 0x48485288
000000D3
