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AM5718: MIPI CSI-2 PHY Intererfaces

Mickael Chouteau36
Prodigy 460 points
Part Number: AM5718

Hi,

I have a question regarding AM5718 MIPI CSI-2 PHY Intererfaces and the simultaneous 4K video inputs support on both.

CSI2_PHY1 with 4 data lanes / 1 clock lane - can that capture 4K@30fps?

CSI2_PHY2 with 2 data lanes / 1 clock lane - can that capture 4K@30fps?

Also, is there a reason why the evaluations boards for the AM5718 do not allow full testing of the MIPI interfaces?

Thanks for your help !

Best Regards,

Mickael

  • 0
    TI__Genius 10180 points

    Mickael,

    CSI2_PHY1 4DL supports 1.5 Gbps * 4 = 6 Gbps; CSI2_PHY2 2DL supports 3 Gbps.

    A typical 4K resolution (3840 x 2160 pixels) at 30 fps and 12 bpp is ~ 3 Gbps, which leaves no overhead for CSI2_PHY2.  CSI2_PHY1 on the other hand will be able to support it with margin.

    I have confirmed internally the reason we did not have example codes was because it was not a use case requirement at the time.

    Take care!

    Best Regards,

    Shiou Mei