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AM6548: Boot up fail after modify EMIF file

Joey Fang
Intellectual 295 points

Part Number: AM6548

Hi, TI team

Currently, I am testing the AM65x industrial development kit.

The SDK version I use is ti-processor-sdk-linux-rt-am65xx-evm-06.02.00.81.

Based on schematic, there are 4GB memory in the AM65x industrial development kit.

I try to reduce the memory size use by OS.

My first step is modify below parameter from 32 to 16 in order to limit the totally memory size to 2GB.

Second, I export the u-boot dtsi file and replace the origin k3-am654-base-board-ddr4-1600MTs.dtsi by this file. The export file as below.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/k3_2D00_am654_2D00_base_2D00_board_2D00_ddr4_2D00_1600MTs.7z

Finally, I compile the r5 u-boot image (tiboot3.bin) and use this image to boot up the IDK.

But, boot up fail.........

The boot up log as below. There are not any message after "Starting ATF on ARM64 core...".

I guess there are other files need to patch except EMIF.

But I don't have any idea........

Could you provide some advice?

Thanks

  • 0
    TI__Guru**** 170880 points

    Hi,

    By reducing the ddr bus width to 16 you cannot access 2GB memory right? 2 ^ 32 is 4GB and 2 ^ 31 is 2GB.
    2 ^ 16 will only get you 64 KB.

    I believe DDR bus width has to be 32 bits.

    Kevin,

    Can you confirm the same.

    Thanks,
    Keerthy

  • 0 in reply to Keerthy J
    Intellectual 295 points

    Hi Keerthy,

    Based on schematic, eight data bus connect to a 1GB Memory.

     

  • 0 in reply to Joey Fang
    TI__Guru**** 170880 points

    Hi,

    Following diff in u-boot directory i got 2GB on AM654-evm:

    diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
    index 37bb92f693..33654083bf 100644
    --- a/board/ti/am65x/evm.c
    +++ b/board/ti/am65x/evm.c
    @@ -43,23 +43,13 @@ int board_init(void)
     
     int dram_init(void)
     {
    -#ifdef CONFIG_PHYS_64BIT
    -       gd->ram_size = 0x100000000;
    -#else
            gd->ram_size = 0x80000000;
    -#endif
     
            return 0;
     }
     
     ulong board_get_usable_ram_top(ulong total_size)
     {
    -#ifdef CONFIG_PHYS_64BIT
    -       /* Limit RAM used by U-Boot to the DDR low region */
    -       if (gd->ram_top > 0x100000000)
    -               return 0x100000000;
    -#endif
    -
            return gd->ram_top;
     }
     
    @@ -70,13 +60,6 @@ int dram_init_banksize(void)
            gd->bd->bi_dram[0].size = 0x80000000;
            gd->ram_size = 0x80000000;
     
    -#ifdef CONFIG_PHYS_64BIT
    -       /* Bank 1 declares the memory available in the DDR high region */
    -       gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
    -       gd->bd->bi_dram[1].size = 0x80000000;
    -       gd->ram_size = 0x100000000;
    -#endif
    -
            return 0;
     }
     
    u-boot log you can see memory is 2GB:

    U-Boot SPL 2019.01-ged486a2e91-dirty (Apr 17 2020 - 16:55:240530)
    SYSFW ABI: 2.7 (firmware rev 0x0013 '19.9.0-v2019.09 (Trific Llama')
    Trying to boot from MMC2
    Starting ATF on ARM64 core...

    NOTICE:  BL31: v2.2(release):ti2019.05-rc1
    NOTICE:  BL31: Built : 03:39:18, Jan  5020
    I/TC:
    I/TC: OP-TEE version: ti2019.05-rc1-dev (gcc version 8.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (m-rel-8.36))) #1 Sun Jan  5 03:38:30 UTC 2020 aarch64
    I/TC: Initialized

    U-Boot SPL 2019.01-ged486a2e91-dirty (Apr 17 2020 - 16:55:240530)
    Trying to boot from MMC2


    U-Boot 2019.01-ged486a2e91-dirty (Apr 17 2020 - 16:55:24 +0530)

    SoC:   AM654 PG 1.0
    Model: Texas Instruments AM654 Base Board
    Board: AM6-COMPROCEVM rev E3
    DRAM:  2 GiB
    MMC:   sdhci@4f80000: 0, sdhci@04FA0000: 1
    Loading Environment from C... OK
    In:    serial
    Out:   serial
    Err:   serial
    Net:   
    Warning: cpsw_nuss@046000000 using MAC address from ROM
    eth0: cw_nuss@046000000, eth1: pruss2_eth
    Hit any key to stop autoboot:  0

    Also kernel meminfo:

    cat /proc/meminfo  
    MemTotal:        1986640 kB
    MemFree:         1761296 kB
    MemAvlable:    1863656 kB

    I have marked the memory read in  Bold. Hope that is what you wanted to accomplish?

    If yes please resolve this thread.

    Regards,
    Keerthy

  • 0 in reply to Keerthy J
    Intellectual 295 points

    Hi Keerthy,

    Thanks for your help.

    However, in future, our customized board just use 16 data bus.

    So, I still need to understand the root cause of boot fail when the EMIF parameter set to 16. 

    Thanks

  • 0 in reply to Joey Fang
    TI__Mastermind 44390 points

    Hi,

    By changing the DDRSS registers to 16-bit, you have reduced the available memory size. However, other parts of code (as shown by Keerthy) were expecting 4GB of memory. Can you try both your original changes for 16-bit data bus and the changes shown by Keerthy and report if you still have boot falures?

    Thanks,
    Kevin

  • 0 in reply to Kevin S
    Intellectual 295 points

    Hi Kevin, Keerthy

    I already patch Keerthy's code to my u-boot project.

    However, it still boot fail.

    Following diff in u-boot directory I changed.

    diff -urNa XXX/u-boot-2019.01+gitAUTOINC+a141f7abfd-ga141f7abfd/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi u-boot-2019.01+gitAUTOINC+a141f7abfd-ga141f7abfd/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi
    --- XXX/u-boot-2019.01+gitAUTOINC+a141f7abfd-ga141f7abfd/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi 2020-01-05 07:31:51.000000000 +0000
    +++ u-boot-2019.01+gitAUTOINC+a141f7abfd-ga141f7abfd/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi 2020-04-17 06:50:48.238973000 +0100
    @@ -1,17 +1,17 @@
    // SPDX-License-Identifier: GPL-2.0+
    /*
    - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
    - * This file was generated by AM65x_DRA80xM_EMIF_Tool_1.98.xlsm
    + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
    + * This file was generated by AM65x_DRA80xM_EMIF_Tool_2.02.xlsm
    * www.ti.com/.../spracj0
    * Configuration Parameters
    * Memory Type: DDR4
    * Data Rate: 1600 MT/s
    * ECC Enabled: No
    - * Data Width: 32 bits
    + * Data Width: 16 bits
    */
    #define DDR_PLL_FREQUENCY 400000000
    #define DDRSS_V2H_CTL_REG 0x000073FF
    -#define DDRCTL_MSTR 0x41040010
    +#define DDRCTL_MSTR 0x41041010
    #define DDRCTL_RFSHCTL0 0x00210070
    #define DDRCTL_ECCCFG0 0x00000000
    #define DDRCTL_RFSHTMG 0x0061008C
    @@ -24,7 +24,7 @@
    #define DDRCTL_INIT4 0x00000020
    #define DDRCTL_INIT5 0x00100000
    #define DDRCTL_INIT6 0x00000480
    -#define DDRCTL_INIT7 0x000004E8
    +#define DDRCTL_INIT7 0x00000497
    #define DDRCTL_DRAMTMG0 0x0C0A1B0D
    #define DDRCTL_DRAMTMG1 0x00030313
    #define DDRCTL_DRAMTMG2 0x0506050A
    @@ -33,10 +33,10 @@
    #define DDRCTL_DRAMTMG5 0x04040302
    #define DDRCTL_DRAMTMG6 0x00000004
    #define DDRCTL_DRAMTMG7 0x00000404
    -#define DDRCTL_DRAMTMG8 0x03030A05
    +#define DDRCTL_DRAMTMG8 0x03030C05
    #define DDRCTL_DRAMTMG9 0x00020208
    #define DDRCTL_DRAMTMG10 0x001C180A
    -#define DDRCTL_DRAMTMG11 0x0E06010E
    +#define DDRCTL_DRAMTMG11 0x1106010E
    #define DDRCTL_DRAMTMG12 0x00020008
    #define DDRCTL_DRAMTMG13 0x0B100002
    #define DDRCTL_DRAMTMG14 0x00000000
    @@ -84,33 +84,33 @@
    #define DDRPHY_DCR 0x0000040C
    #define DDRPHY_DTPR0 0x041A0B06
    #define DDRPHY_DTPR1 0x28140000
    -#define DDRPHY_DTPR2 0x0034E255
    -#define DDRPHY_DTPR3 0x01D50800
    +#define DDRPHY_DTPR2 0x0034E300
    +#define DDRPHY_DTPR3 0x02800800
    #define DDRPHY_DTPR4 0x31180805
    #define DDRPHY_DTPR5 0x00250B06
    #define DDRPHY_DTPR6 0x00000505
    #define DDRPHY_ZQCR 0x008A2A58
    #define DDRPHY_ZQ0PR0 0x000077DD
    -#define DDRPHY_ZQ1PR0 0x000077DD
    +#define DDRPHY_ZQ1PR0 0x00007799
    #define DDRPHY_MR0 0x00000214
    #define DDRPHY_MR1 0x00000501
    #define DDRPHY_MR2 0x00000000
    #define DDRPHY_MR3 0x00000020
    #define DDRPHY_MR4 0x00000000
    #define DDRPHY_MR5 0x00000480
    -#define DDRPHY_MR6 0x000004E8
    +#define DDRPHY_MR6 0x00000497
    #define DDRPHY_MR11 0x00000000
    #define DDRPHY_MR12 0x00000000
    #define DDRPHY_MR13 0x00000000
    #define DDRPHY_MR14 0x00000000
    #define DDRPHY_MR22 0x00000000
    -#define DDRPHY_VTCR0 0xF3C32028
    +#define DDRPHY_VTCR0 0xF3C32017
    #define DDRPHY_DX8SL0PLLCR0 0x021c4000
    #define DDRPHY_DX8SL1PLLCR0 0x021c4000
    #define DDRPHY_DX8SL2PLLCR0 0x021c4000
    #define DDRPHY_DTCR0 0x8000B1C7
    #define DDRPHY_DTCR1 0x00010236
    -#define DDRPHY_ACIOCR0 0x30070000
    +#define DDRPHY_ACIOCR0 0xF0070000
    #define DDRPHY_ACIOCR3 0x00000001
    #define DDRPHY_ACIOCR5 0x04800000
    #define DDRPHY_IOVCR0 0x0F0C0C0C
    @@ -122,14 +122,14 @@
    #define DDRPHY_DX1GCR1 0x00000000
    #define DDRPHY_DX1GCR2 0x00000000
    #define DDRPHY_DX1GCR3 0x00000000
    -#define DDRPHY_DX2GCR0 0x40700204
    -#define DDRPHY_DX2GCR1 0x00007FFF
    -#define DDRPHY_DX2GCR2 0x00000000
    -#define DDRPHY_DX2GCR3 0xFFC0010B
    -#define DDRPHY_DX3GCR0 0x40700204
    -#define DDRPHY_DX3GCR1 0x00007FFF
    -#define DDRPHY_DX3GCR2 0x00000000
    -#define DDRPHY_DX3GCR3 0xFFC0010B
    +#define DDRPHY_DX2GCR0 0x40703220
    +#define DDRPHY_DX2GCR1 0x55556000
    +#define DDRPHY_DX2GCR2 0xAAAA0000
    +#define DDRPHY_DX2GCR3 0xFFE18587
    +#define DDRPHY_DX3GCR0 0x40703220
    +#define DDRPHY_DX3GCR1 0x55556000
    +#define DDRPHY_DX3GCR2 0xAAAA0000
    +#define DDRPHY_DX3GCR3 0xFFE18587
    #define DDRPHY_DX4GCR0 0x40703220
    #define DDRPHY_DX4GCR1 0x55556000
    #define DDRPHY_DX4GCR2 0xAAAA0000
    @@ -157,6 +157,7 @@
    #define DDRPHY_DX8SL0DXCTL2 0x00141830
    #define DDRPHY_DX8SL1DXCTL2 0x00141830
    #define DDRPHY_DX8SL2DXCTL2 0x00141830
    -#define DDRPHY_DX8SL0DQSCTL 0x01264000
    -#define DDRPHY_DX8SL1DQSCTL 0x01264000
    -#define DDRPHY_DX8SL2DQSCTL 0x01264000
    +#define DDRPHY_DX8SL0DQSCTL 0x01264300
    +#define DDRPHY_DX8SL1DQSCTL 0x01264300
    +#define DDRPHY_DX8SL2DQSCTL 0x01264300
    +
    diff -urNa XXX/u-boot-2019.01+gitAUTOINC+a141f7abfd-ga141f7abfd/board/ti/am65x/evm.c u-boot-2019.01+gitAUTOINC+a141f7abfd-ga141f7abfd/board/ti/am65x/evm.c
    --- XXX/u-boot-2019.01+gitAUTOINC+a141f7abfd-ga141f7abfd/board/ti/am65x/evm.c 2020-01-05 07:31:51.000000000 +0000
    +++ u-boot-2019.01+gitAUTOINC+a141f7abfd-ga141f7abfd/board/ti/am65x/evm.c 2020-04-20 06:09:46.809990240 +0100
    @@ -43,22 +43,15 @@

    int dram_init(void)
    {
    -#ifdef CONFIG_PHYS_64BIT
    - gd->ram_size = 0x100000000;
    -#else
    +
    gd->ram_size = 0x80000000;
    -#endif
    +

    return 0;
    }

    ulong board_get_usable_ram_top(ulong total_size)
    {
    -#ifdef CONFIG_PHYS_64BIT
    - /* Limit RAM used by U-Boot to the DDR low region */
    - if (gd->ram_top > 0x100000000)
    - return 0x100000000;
    -#endif

    return gd->ram_top;
    }
    @@ -70,12 +63,6 @@
    gd->bd->bi_dram[0].size = 0x80000000;
    gd->ram_size = 0x80000000;

    -#ifdef CONFIG_PHYS_64BIT
    - /* Bank 1 declares the memory available in the DDR high region */
    - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
    - gd->bd->bi_dram[1].size = 0x80000000;
    - gd->ram_size = 0x100000000;
    -#endif

    return 0;
    }

  • 0 in reply to Joey Fang
    TI__Guru**** 170880 points

    Hi,

    U-boot changes look fine to get the memory to 2GB.

    Kevin,

    Can you confirm that DDR side changes are fine?

    - Keerthy

  • 0 in reply to Keerthy J
    Intellectual 295 points

    Hi Kevin,

    Do you have any further information?

    Thanks

  • 0 in reply to Joey Fang
    TI__Mastermind 44390 points

    Hi,

    My understanding is that this has been resolved by following the information documented in section 2.3.3 of the XLS user guide (i.e, changing the number of column bits to 9,  and updating the address mapping in the XLS accordingly). 

    Closing this ticket.

    Best regards,
    Kevin