Power up problem with eZdsp USb stick 5505 standalone

Hi Arvid,

You said that the program in flash executes if you connect the eZdsp to CCS and press run. This does sound like an initialization problem.

What happens if you connect to the target without a GEL file and then try to run?

Double click on the Target Configuration, click on the Advanced tab at the bottom of the Target Configuration window, click on C55xx, delete path in the "initialization script" field, save, and then connect. See screen shot below.

If the project fails to run correctly, then it tells me that you are performing some initialization in the GEL file that you are not performing in your bootloaded program.

Regards,
Mark

Hi Mark,

Thanks for the reply. I tried this, and indeed when i run the program, it does not work the first time when connected to CCS if the gel file is not set in the 'init. script' field. However, even if i don't use the gel file, i can get it to run in emulation fine by first doing a CPU reset, then pressing run.

So I've tried to think what the pressing the CPU reset button, and the gel file instructions in OnRestart() or OnTargetConnect() (and power-cycling quickly in standalone) have in common that makes it work.

I tried adding the contents of the gel's OnRestart() function:

    /* Disable interrupts */
    *(int*)0x0003 = *(int*)0x0003 | 0x0800; // Set INTM
    *(int*)0x0000 = 0;      // Clear IER0
    *(int*)0x0000 = 0;      // Clear IER1

  to the beginning of my reset_isr (which is the code entry point) as:

        *port(#0x0003) = *port(#0x0003) | #0x0800
        *port(#0x0000) = #0
        *port(#0x0000) = #0

but with no luck. Still working on trying other stuff - like adding in

Peripheral_Reset()
{
    int i;

    *(short *)PSRCR@IO = 0x0020;
    *(short *)PRCR@IO  = 0x00BB;

    for(i=0;i<0xff;i++);
    *(short *)IVPD@data = 0x027F; // Load interrupt vector pointer
    GEL_TextOut("Reset Peripherals is complete.\n");
}

The PSRCR and PRCR are already taken care of, but I can't figure out how to add the IVPD set because I can't find the address of IVPD anywhere in the documentation. I found this

http://processors.wiki.ti.com/index.php?title=55x_FAQ&DCMP=DSP_C550x&HQS=Other+PR+c5505-prfaq2#How_do_I_change_stack_modes.3F

but I'll confess i don't really understand it.

Yeah - it really seems to be that it needs the reset before running.

I'm modifying the GEL file, then launching the Target Config with the GEL file in use, then connecting to the target, NOT loading a program, (i.e. so it uses the one I've flashed) then pressing Run, and here are the results:

• GEL_Reset() only commented out in the GEL file: program does not work correctly
• every function call except GEL_Reset() commented out in GEL file: program works fine

so it seems like it needs the reset after powering up and that is it. Weird, huh?

If I put a bunch of nop_16's at the beginning of the reset_isr (code entry point) the audio will usually randomly start working 10 sec to 1 minute after I power it on when in standalone, which i find quite strange.

Hi Arvid,

These tips might help you get your program running correctly in stand-alone mode.

* Note that GPIO26 is tied to the RESET signal of the codec on the VC5505 eZdsp.

From the VC5505 Datasheet: "After the boot process is complete, the peripheral clocks will be off and all domains in the ICR, except the CPU domain, will be idled (this includes the MPORT and HWA). The user must enable the clocks to the peripherals and CPU ports that are going to be used. The peripheral clock gating control registers (PCGCR1 and PCGCR2) are used to enable and disable the peripheral clocks."

During initialization...

* Take all used ports out of IDLE by clearing the bits of the ICR (0x0001 @ DATA). See Section 5.5 Clock Management of the TMS320VC5505 DSP System User's Guide

* Unclockgate peripherals that will be used by clearing the bits of the PCGCR1 & 2 registers. See Section 5.5.2.1 Peripheral Clock Gating Configuration Registers (PCGCR1 and PCGCR2) [1C02 - 1C03h] of the TMS320VC5505 DSP System User's Guide

* Don't forget to configure the PLL for your desired SYSCLK speed (this is done by the GEL file during debugging)

Let me know how it goes,
Mark

I think I already have that all accounted for - as I say, I'm using the initialization routines directly from the Audio Filter Demo here: http://code.google.com/p/c5505-ezdsp/. I could easily be wrong, but I think it does everything you suggested. But maybe not in the right order? Here's what is happening code-wise:

The code entry point is this reset_isr (below), with the only thing changed from the example being comments and the highlighted line I added today when trying new things to fix it. This is followed by the initialization functions in main(). I also tried running with the code entry point at _c_Int00, but that did not run at all.

;****************************************************************************
;* Reset from vector.asm
;****************************************************************************

        .text
        .def reset_isr
        .ref _c_int00
       
        .align 2       
reset_isr:

        ;repeat(#0xFFFF)
        ;NOP_16

        ; atp added these lines:
        ;*port(#0x0003) = *port(#0x0003) | #0x0800
        ;*port(#0x0000) = #0
        ;*port(#0x0000) = #0
       
    ;    *port(#0x1C01) = #0x0                ; Clear idles
        bit (ST1, #11) = #1                    ; Disable interrupts
        @IVPD_L = #(_RST >> 8) || mmap()
        @IVPH_L = #(_RST >> 8) || mmap()
           bit (ST3,#7) = #0        ; Clear bus error interrupts
           bit (ST3,#2) = #1        ; shut off clockout port
           bit (ST1,#13) = #0        ; shut off XF port

        @#IFR0_L = #0xffff || mmap() ; clear all pending interrupts
        @#IFR1_L = #0xffff || mmap()

        *port(#IDLE_ICR) = #(RESERVED_ICR|IPORT_IDLE|HWA_IDLE|DPORT_IDLE)  
        idle

;**********************************************************************************
;     Reset all peripherals
;**********************************************************************************
    *port(#0x1C04) = 0x20 ; PSRCR
    nop_16
    *port(#0x1C05) = 0x00BB    ; Reset all peripherals - PRCR
    nop_16

;**********************************************************************************
;     Enable EMIF
;**********************************************************************************

    *port(IDLE_PCGCR) = #0x0
   
    ;added by Arvid just in case needed
    *port(IDLE_PCGCR_MSW) = RESERVED_PCGCR_MSW ;should set all non-reserved bits to 0

    ;/* Config EMIF - System Control Regsiter */
    *port(#0x1C33) = #0x0 

    ;// for SRAM in memory card (Async_CE1)
    ;/* Config EMIF - ASYNC Regsiters */
    *port(#0x1004) = #0x0080    
    *port(#0x1005) = #0x00E4    

    ;/* Configure as 16-bit data bus */   
    ;// Async4 ==> Async_CE1 (SRAM)   
    *port(#0x101C) = #0x40AD    
    *port(#0x101D) = #0x0020    

    ;// Async3 ==> Async_CE0(Flash)
    *port(#0x1018) = #0xFFFD    
    *port(#0x1019) = #0x3FFF    


    ;// do not assign Async_CE0 and Async_CE1 for NAND
    *port(#0x1060) = #0x0003    
   
    ;// Turn off page mode for all Chip Selects
    *port(#0x1068) = #0xFCFC    
    *port(#0x1069) = #0xFCFC    

    goto    _c_int00

And here is what happens at the beginning of main() in main_bypass1.c:

    {
    InitSystem();
    ConfigPort();

    SYS_GlobalIntEnable();
    reset_RTC();   
   
    IER0 = 0x0110;      // enable dma, timer int     
    IER1 = 0x0004;      // enable RTC int

    setDMA_address();
    //set_i2s0_master();
    set_i2s0_slave();
    AIC3254_init();

    //PLL_98MHz(); //for some reason the example inits the PLL a second time here
    //I don't know why - but it behaves the same way (ie never boots properly standalone) with or without it commented out.
    //Despite the name of the function, it does not set the PLL to 98MHz unless PLL_98M == 1,
    //which is exactly the same thing InitSystem() does. In this project PLL_100M = 1 and PLL_98M = 0.

    enable_i2s0();
    enable_dma_int();
    set_dma0_ch0_i2s0_Lout();
    set_dma0_ch1_i2s0_Rout();
    set_dma0_ch2_i2s0_Lin();
    set_dma0_ch3_i2s0_Rin();
    enable_rtc_second_int();

...}

And here are all the function definitions for the above stuff in main that are in the main_bypass1.c file:

void InitSystem(void)
{
    Uint16 i;
// PLL set up from RTC
    // bypass PLL
    CONFIG_MSW = 0x0;

#if (PLL_100M ==1)
    PLL_CNTL2 = 0x8000;
    PLL_CNTL4 = 0x0000;
    PLL_CNTL3 = 0x0806;
    PLL_CNTL1 = 0x82FA;
   
#elif (PLL_12M ==1)
    PLL_CNTL2 = 0x8000;
    PLL_CNTL4 = 0x0200;
    PLL_CNTL3 = 0x0806;
    PLL_CNTL1 = 0x82ED;
#elif (PLL_98M ==1)   
    PLL_CNTL2 = 0x8000;
    PLL_CNTL4 = 0x0000;
    PLL_CNTL3 = 0x0806;
    PLL_CNTL1 = 0x82ED;

#elif (PLL_40M ==1)       
    PLL_CNTL2 = 0x8000;
    PLL_CNTL4 = 0x0300;
    PLL_CNTL3 = 0x0806;
    PLL_CNTL1 = 0x8262;   
#endif

    while ( (PLL_CNTL3 & 0x0008) == 0);
    // Switch to PLL clk
    CONFIG_MSW = 0x1;
   
    //test from asm file
    //asm("*port(#IDLE_ICR) = #(RESERVED_ICR|IPORT_IDLE|HWA_IDLE|DPORT_IDLE)");

// clock gating
// enable all clocks
    IDLE_PCGCR = 0x0;
    IDLE_PCGCR_MSW = 0xFF84;
   

// reset peripherals
    PER_RSTCOUNT = 0x02;
    PER_RESET = 0x00fb;   
    for (i=0; i< 0xFFF; i++);
}

void ConfigPort(void)
{
    Int16 i;
    //  configure ports
    PERIPHSEL0 = 0x6900;        // parallel port: mode 6, serial port1: mode 2

    for (i=0; i< 0xFFF; i++);
}


void SYS_GlobalIntEnable(void)
{
    asm(" BIT (ST1, #ST1_INTM) = #0");
}

void SYS_GlobalIntDisable(void)
{
    asm(" BIT (ST1, #ST1_INTM) = #1");
}

Thanks again!

Arvid

I still have not gotten anywhere with this, also tried with several Rev D eZdsp 5505's, and they show the same problem (need to be turned on and off twice in rapid succession to boot properly from flashed program). Tried all sorts of changes, including initialization routines in C instead of assembly - no luck.

Does anyone have code that reliably starts a 5505 eZdsp when flashburned and running standalone? If so, how did you do it? I can't for the life of me get it to work.

Awesome!

Thanks for posting your solution - very strange fix.

Maybe the DSP was writing to the codec before it was ready?

Regards,
Mark