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CCS/TMDSICE3359: Setup of DDR3 when debugging

John Beard
Intellectual 390 points

Part Number: TMDSICE3359
Other Parts Discussed in Thread: AM3359

Tool/software: Code Composer Studio

I am using the ICEv2 (TMDSICE3359) to debug a program with an XDS100v3 probe.

If I debug without setting any GEL file, I cam load the PDK examples (and my own program) into the EMIF DDR3 RAM located in memory at 0x80000000. Notably, there does not appear to be any configuration of this DDR RAM, and yet it works.

If I set the GEL file at ccs_base/emulation/boards/ice_am3359/gel/TMDXICE3359.gel, the GEL runs OK and then the file load into DDR also works.

Why does this work at all without a GEL file to do DDR/EMIF init?

  • 0
    TI__Mastermind 30118 points

    Hi John,

    >>  there does not appear to be any configuration
    >> Why does this work at all without a GEL file to do DDR/EMIF init?

    Are the EMIF registers the same with and without GEL?

    Are you unintentionally booting (SBL) from some source (e.g. McSPI) before connecting via JTAG without GEL?

    When the GEL file is executed, do you see the output "DDR PHY Configuration done "? This is output at the end of the GEL function "DDR3_EMIF_Config()". The EMIF registers are configured for DDR in this function. Below is a portion of the GEL function call graph which is executed on connecting to the target:

    OnTargetConnect()
    AM3359_ICE_Initialization()
        DDR3_EMIF_Config()

    You should be able to look through DDR3_EMIF_Config() to determine how the EMIF registers are configured. You can then compare against the case of power-cycling the board and connecting via JTAG without GEL to see if the register settings are the same.

    Regards,
    Frank

  • 0 in reply to Frank Livingston
    Intellectual 390 points

    Hi Frank,

    It looks like you are right, something seems to have booted the device on power-up.

    At 0x402f0400 (OCMC SRAM) there is a program, which must have been loaded from somewhere. However, there isn't an SD card in the slot, and I ran the isdk_spi_flasher program to (hopefully clear out the flash memory), which reported success.

    On reading the flash with the GPMC demo project, it seems to be full of valid program - shouldn't it be 0xFF after the isdk_spi_flasher runs?

    Also, can you only open the flash if the J5 pins are jumpered between 1-2? When 2-3, the flash cannot be opened.

  • 0 in reply to John Beard
    TI__Mastermind 30118 points

    Hi John,

    >> I ran the isdk_spi_flasher program
    >> On reading the flash with the GPMC demo project

    Are you referring to one of the GPMC example projects documented here? 
    http://software-dl.ti.com/processor-sdk-rtos/esd/docs/06_03_00_106/rtos/index_device_drv.html#id247

    Note GPMC is connected to the NOR flash, not the SPI flash.

    >> it seems to be full of valid program - shouldn't it be 0xFF after the isdk_spi_flasher runs?

    Please try the second GPMC example program (GPMC NOR/NAND test application) to erase the NOR flash. Yes, I believe it should read as 0xFF when erased.

    >> can you only open the flash if the J5 pins are jumpered between 1-2? When 2-3, the flash cannot be opened.

    I notice these instructions for erasing the SPI flash indicate J5 1-2 should be jumpered:

    Please see additional details concerning ICEv2 boot configuration in spruip3.pdf, 4.1 Boot Configuration. 

    Regards,
    Frank