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CCS/AM5716: McASP4 does't receive data in loopback mode or from an external device

Part Number: AM5716
Other Parts Discussed in Thread: SYSBIOS,

Tool/software: Code Composer Studio

Hi,

I'm working on the TI example project (MCASP_DeviceLoopback_idkAM571x_c66ExampleProject) generated with pdk_am57xx_1_0_11 (CCS v8.3.1, SYSBIOS 6.52.0.12).

In this project, the default device is McASP3 and the loop works fine with both internal level (McASP module-level) and chip I/O-level loopback modes. (IOLBEN=0 and IOLBEN=1). (AXR0=output, AXR1= input)

In my board, Sitara AM5716 is connected to a PLD with McASP4. I've made all the settings to move from McASP3 to McASP4. When I make the loop at the internal level (McASP module-level), the output data are equal to the input data and the test passes. From this (path DSP-EDMA-McASP4-EDMA-DSP), I suppose that the registers for EDMA, IRQ_CROSSBAR, DMA_CROSSBAR, DSP_IRQ are correct.

The problem is in the chip I/O-level loopback mode: the input data are all 0s. At the output pin (AXR0) I see with an oscilloscope the data as expected.

I suppose I missed a configuration when I moved from McASP3 to McASP4, but I can't find it.

Can you help me.

Thank you.

Francesco

  • Hi Francesco,

    Did you update the pad config register to set pin mux for McASP4 pins?

    Regards,
    Stanley

  • Hi Stanley,

    I wrote in the registers 0x4a003734 (ACLKX), 0x4a003738 (FSX), 0x4a00373c (AXR0) and 0x4a003740 (AXR1) to set the pin muxes:

    // **** McASP4 ****
            /* McASP4 Module Control */
            HW_WR_FIELD32(CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP4_CLKCTRL_REG, \
                    CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP4_CLKCTRL_REG_MODULEMODE, \
                    CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP4_CLKCTRL_REG_MODULEMODE_ENABLE);
            while ((HW_RD_REG32(CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP4_CLKCTRL_REG) & CM_L4PER2_MCASP4_CLKCTRL_MODULEMODE_MASK) != \
                    CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP4_CLKCTRL_REG_MODULEMODE_ENABLE) ;
    
         /* PAD IO Config for MCASP4 pins - ACLKX, AFSX, AXR0, AXR1*/
            HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP4_ACLKX, \
                CSL_CONTROL_CORE_PAD_IO_PAD_MCASP4_ACLKX_MCASP4_ACLKX_MUXMODE, \
                0x0);
            HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP4_FSX, \
                    CSL_CONTROL_CORE_PAD_IO_PAD_MCASP4_FSX_MCASP4_FSX_MUXMODE, \
                0x0);
            HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP4_AXR0, \
                    CSL_CONTROL_CORE_PAD_IO_PAD_MCASP4_AXR0_MCASP4_AXR0_MUXMODE, \
                0x0);
            HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP4_AXR1, \
                    CSL_CONTROL_CORE_PAD_IO_PAD_MCASP4_AXR1_MCASP4_AXR1_MUXMODE, \
                0x0);
            HW_WR_FIELD32(CSL_DSP_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_MCASP4_AXR1, \
                    CSL_CONTROL_CORE_PAD_IO_PAD_MCASP4_AXR1_MCASP4_AXR1_INPUTENABLE, \
                CSL_CONTROL_CORE_PAD_IO_PAD_MCASP4_AXR1_MCASP4_AXR1_INPUTENABLE_ENABLE);

    After that I used TI driver to configure the McASP4.

    regards,

    Francesco

  • Is there any external device which might be driving the McASP4 AXR1 pin low?

  • Hi Stanley,

    McASP4 AXR1 is connected to a PLD pin which is set in high impedence.

    With the I/O loopback, it still doesn't work  which is strange because I've recently made an external loop through the PLD and this works.

    At this point for me the issue is solved, even though the I/O loopback is unclear.

    If you don't have any other suggestion or test to do we can close this issue.

    regards

    Francesco