Hi,
DDR3 800 slew rate is slow can not match JEDEC standards.
Could you provide what is DQS slew rate for the AM3352 can accept?
What is the DDR rising time/falling time for AM3352
Thanks
Daniel
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Hi,
DDR3 800 slew rate is slow can not match JEDEC standards.
Could you provide what is DQS slew rate for the AM3352 can accept?
What is the DDR rising time/falling time for AM3352
Thanks
Daniel
Daniel, the AM335x DDR slew rate can be adjusted in the DDR PHY. Please use the AM335x EMIF tool http://www.ti.com/lit/pdf/sprack4 to adjust this. The spreadsheet has the "slow" slew rate as the recommended setting, but if you can adjust this by changing the slew setting for clk, addr/ctrl, and data/strobe.
I'm not sure why your design is not meeting the spec. Where on the trace are you probing the signal? You may also need to adjust some of your IO characteristics (output impedance or ODT). Are you using the default values in the spreadsheet? Also, ensure you have followed all of the design and routing guidelines in the AM335x datasheet.
Regards,
James