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AM4377: EtherCAT input latch ESC time

Liliane Paradise
Intellectual 320 points
Part Number: AM4377

Hello community,

Our team is currently working on implementing the EtherCAT Semiconductor Device Profile on a Sitara AM4377 processor. For this purpose, we use the Beckhoff slave stack code, together with the TI drivers and our product firmware. Since we would like to support Distributed Clocks, we need to implement the Object Dictionary Entry F6F2 Input Latch ESC Timestamp. To our best understanding, the function void bsp_get_latch0_posedge_time(PRUICSS_Handle pruIcssHandle, uint32_t *systime_low, uint32_t *systime_high) (tiescbsp.c/.h) should do the job by reading the ESC Register ESC_ADDR_LATCH0_POS_EDGE. However, this register always holds the value 0, both for the Low Word, as also for the High Word.
We are testing with TwinCAT, where we ensure that the operation mode is DC and that SYNC0 is enabled. The sync unit cycle time is set to the sync unit cycle time of 4 ms. Does anybody have a clue why this register doesn't hold the actual input latch time?

Many thanks in advance,

Liliane

  • 0
    TI__Mastermind 43296 points

    Hi Liliane,

    Have you checked these latch related registers starting from 0x09A8, and event request register 0x210, 0x220?

    Regards,

    Garrett

  • 0 in reply to Garrett Ding
    Intellectual 320 points

    Hello Garrett,

    Thank you for your response. I checked the registers, and I noticed that even if I set Latch0 control (0x09A8) to single event via TwinCAT (I verified by reading the value 0x3 from the register), the Latch0 Status (0x09AE) register stays at zero. This would either mean continuous mode (not the case), or that the positive edge is not detected, which would also explain why the time is not captured. When reading the event request register, I read the value 0x30 in register 0x210 and 0xC in register 0x220. The first means, that there are no changes in DC latch inputs. How can I interpret this? The second means that the states of DC Sync 0 and 1 are on 1, does that mean that I am receiving the interrupts?
    I general, I tested that the Sync IRQ works, so I am kind of sure that I am actually receiving these interrupts. Do you have any other inputs based on the above information?

    Thank you in advance,

    Liliane

  • 0 in reply to Liliane Paradise
    TI__Mastermind 43296 points

    Hi Liliane,

    Please refer to the thread for the latch register configuration and pin routing. Note, the thread was discussing the AM335x but the concept is the same. 

    Regards,

    Garrett