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TDA4VM: PDN DC DROP

YUTAI LI1
Intellectual 400 points
Part Number: TDA4VM
Other Parts Discussed in Thread: DRA77P

Hi TI Support Team 

From application noets:  "Max PCB static/DC voltage drop (IRd) budget can be relaxed to 7.5 % of supply voltage when using PMICs with remote sensing at the load as measured from PMIC’s power inductor and filter capacitor node to Device’s supply input including any ground return losses."

Question:

Why we need use 7.5%  not 5% / 10% ......when we use PMIC with remote sense ? 

Thanks

Yutai

  • 0
    TI__Guru 54472 points

    Yutai,

    What application note are you referencing?

    The point of this statement is that the DC voltage drop from the PMIC output to the SoC input is accounted for with the remote sense.  If (say) the voltage drop is 50 mV then the PMIC output will increase by ~50 mV (+/- the PMIC accuracy) to keep the DC level at the SoC balls at the desired set point.

    Thanks,

    Kyle

  • 0 in reply to kcastille
    Intellectual 400 points

    Hi Kyle

    The recomment info from your  "J7ES Prelim PDN PI Recmds v1.2.pdf". I can't post it in here because it will be some NDA issue.

    I can send mail to you later.

    Thanks

    Yutai

  • 0 in reply to YUTAI LI1
    TI__Guru 54472 points

    Yutai,

    That number is not very important if remote sense is used.  If you refer to the DRA77P data manual on ti.com, refer to section 7.2.3 Step 3: Static Analysis.  This gives a detailed description of why the static IR drop should be minimized.  

    Also, refer to section 7.3.1 General Constraints and Theory.  This again distinguishes between an implementation with or without remote sense.

    The important part that should be met for a given design is summarized in  Table 7-3. Recommended PDN Characteristics and EVM Decoupling Capacitors.  The Static Max Reff is defined with a requirement that remote sense is used.  This is the value that is simulated and validated by TI.  If this value is met then the 1.5 vs 5 vs 7.5% DC IR drop is taken care of.

    Regards,

    Kyle

  • 0 in reply to kcastille
    Intellectual 400 points

    Hi Kyle

    I know we need use min DC (IR) Drop for PI simulaiton. 

    My query is that Why we need use 7.5%  not 5% / 10% / 20% ......when we use PMIC with remote sense. Is it releate TI PMIC accuracy ?

    Because we know the PMIC output will increase by  xx mV o keep the DC level at the SoC balls at the desired set used remote sense. 

    But we dont know why we need choose 7.5% threshold value for PMIC with remote sense. 

     

    Thanks

    Yutai

  • 0 in reply to YUTAI LI1
    TI__Guru 54472 points

    Yutai,

    The 7.5% is related to the maximum current that can theoretically be consumed by a supply domain, versus the maximum DC impedance allowed for PI simulation.  

    Regards,

    Kyle 

  • 0 in reply to kcastille
    Intellectual 400 points

    Kyle

    Sorry, I still not understand your point about the 7.5% is max voltage drop. Can you please share more info about why we need choose 7.5%?

    In other words the power voltage DC drop to 10% x VDD , is it possible to increase voltage from PMIC.

    Thanks

    Yutai 

  • 0 in reply to YUTAI LI1
    Intellectual 400 points

    Any update from your side? Kyle

  • 0 in reply to YUTAI LI1
    TI__Expert 6995 points

    Your outstanding questions:

    1. "Why we need use 7.5%  not 5% / 10% / 20% ......when we use PMIC with remote sense. Is it releate TI PMIC accuracy ?"

    Ans: The 7.5% recommendation was derived after reviewing TI PMIC buck converter's remote sensing & DC offset compensation ranges across typical PMIC PNs recommended forJacinto SoC PDNs. It was determined that a 7.5% recommendation provides:
    1.) DC offset voltage compensation range within PMIC specifications for stable operation.
    2.) Robust PCB routing with sufficient routing area to avoid unnecessarily large IR/voltage drops due to restricted PCB routing that puts too much demand on the local decoupling caps while the buck converter is reacting to increase load as part of the regulation loop. This can lead to excessive power supply transient noise dips that can hang the processor under heavy loads.

    2. "In other words the power voltage DC drop to 10% x VDD , is it possible to increase voltage from PMIC."

    Ans: It all depends on the buck converter's DC offset range capability and regulation loop will compensates as much as possible up to a limit which then leads to dropping out of regulation. TI does not recommend restricting PCB power routing that could lead to 10% voltage drop and relying on DC voltage compensation, see item 2 above.