Source clock for ARMSS (ARM926EJ-S).

Hello Andrew,

The TMS320DM36x User Guide provides guidance on the questions you listed:

1) See section 9.12.19 Peripheral Clock Control (PERI_CLKCTL) Register

2) Correct, as discussed in section 6.2 PLLC1 Controller using the PLLEN register

3) See section  6.5.2 Changing Divider / Multiplier Ratios

For your last two questions, I'm not sure of the context in which you refer to PPLCTL or PPLRST.

Without knowing which document or peripheral I can only say that PPLRST  = 1 puts the peripheral in reset state and when set to 0

the peripheral moves out of the reset state.

Marcus

Hello.

My dm365 board runs Linux OS.

Linus OS uses PLL2 as clock reference for ARMSS (ARM926EJ-S).

PLL2SYSCLK2 feeds ARMSS.

Default Linux configuration:

prediv = 7

mult = 99

postdiv = 0

PLL2_SYSCLK2 = 1

ARM core freq = 24 / (7+1) * (99*2) * (0+1) / (1+1) = 297 MHz

I want to change PLL2 configuration at work time.

I follows steps from sprufg5a.pdf documentation, chapter 6.5 "PLL Configuration".

But nex step wholly hangs my system:

* In PLLCTL, write PLLEN = 0

Code in C language looks like:

__raw_writel(ctrl, pll->base + PLLCTL);

where ctrl = 0x50;

Please advice me in PLL2 configuration.

After above command Linux kernel completely stops.

Board information: DM365 EVM Rev E Thanks!

So the first step you attempt is change to PLL bypass mode, where PLLCTL is set to 0x50.

Why 0x50 and not 0x00?

You are writing to reserved bit fields (bit 31-6, 4 Reserved - Any writes to these bit(s) must always have a value of 0.

Hello.

Thanks for reply.

1. I read current status of PLLCTL register.

2. Set PLLEN bit to 0.

3. Write it back to PLLCTL.

/*
 * Read PLL control register.
 */
    ctrl = __raw_readl(pll->base + PLLCTL);
    dprintk("PLL control register = 0x%x (%d).\n", ctrl, ctrl);

Kernel put out message:

PLL control register = 0x51, (81).

    /*
     * Write PLLEN = 0. Swith to bypass mode.
     */
    ctrl &= ~PLLCTL_PLLEN;
   dprintk("Write new PLL control register = 0x%x (%d). Set PLLEN = 0.\n", ctrl, ctrl);

Kernel put out message:

Write new PLL control register = 0x50 (80). Set PLLEN = 0.

Next command hangs system:

    __raw_writel(ctrl, pll->base + PLLCTL);

Try writing 0x00 instead of 0x50?.

Hello.

Thank you for help!

The main problem was:

ARM core must run at rate > PLLC1SYSCLK4.

sprufg5a.pdf:

9.12.19 Peripheral Clock Control (PERI_CLKCTL) Register

ARM926 clock source selection
When changing the source clock (either 0 to 1 or 1 to 0), ARM926 clock frequency must be  CFG/DMA bus clock frequency (PLLC1SYSCLK4).

In my case ARM core switched to PLL2 bypass frequency, wich is far smaller that PLLC1SYSCLK4 (121500kHz).