TCI6638K2K: 6638k2k: Keystone2 - SRIO inconsistency between PDK support and specifications

Daniel Costin

Part Number: TCI6638K2K

Hi,

In SPRUGW1C manual it is listed that line rate can be set to full, half, quarter ,eigth. In CSL I see there is no support for eighth.

Starting from ref_clk and following to obtain a specific link rate in Gbps we should set MPY and line rate.
In CSL we have:

typedef enum
{
CSL_SERDES_LANE_FULL_RATE = 0,
CSL_SERDES_LANE_HALF_RATE = 1,
CSL_SERDES_LANE_QUARTER_RATE = 2
} CSL_SERDES_LANE_CTRL_RATE;

We are using pdk_k2hk_4_0_14.

over 5 years ago

0 Daniel Costin over 5 years ago

Intellectual 610 points

0 lding over 5 years ago in reply to Daniel Costin

TI__Guru* 95265 points

Hi,

The Keystone I and Keystone II Serdes are totally different. The Table 3-7 above is for Keystone I device. For 6638K2K, the CSL is correct:

typedef enum
{
CSL_SERDES_LANE_FULL_RATE = 0,
CSL_SERDES_LANE_HALF_RATE = 1,
CSL_SERDES_LANE_QUARTER_RATE = 2
} CSL_SERDES_LANE_CTRL_RATE;

There is no 1/8 rate. You can also refer to Keystone II Serdes UG: http://www.ti.com/lit/ug/spruho3a/spruho3a.pdf. The rate is controlled by:

0x1FE0 LANE1CTL_STS Lane 1 Control and status Section 17.4.1
0x1FE4 LANE2CTL_STS Lane 2 Control and status Section 17.4.1
0x1FE8 LANE3CTL_STS Lane 3 Control and status Section 17.4.1
0x1FEC LANE4CTL_STS Lane 4 Control and status Section 17.4.1

Regards, Eric

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TCI6638K2K: 6638k2k: Keystone2 - SRIO inconsistency between PDK support and specifications